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Method for manufacturing film transistor plane indicator

A technology of thin-film transistors and flat-panel displays, which is applied in semiconductor/solid-state device manufacturing, static indicators, instruments, etc., to achieve the effect of simplifying the manufacturing process

Inactive Publication Date: 2006-02-01
AU OPTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Although the above-mentioned traditional methods are used to manufacture thin film transistors, there is still room for improvement in the manufacturing process of thin film transistors.

Method used

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  • Method for manufacturing film transistor plane indicator
  • Method for manufacturing film transistor plane indicator
  • Method for manufacturing film transistor plane indicator

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0023] Figure 2A-2D It is a top view of the manufacturing process of the first embodiment of the present invention. Figure 3A-3D It is a sectional view of the manufacturing process of the first embodiment of the present invention. Figure 3A-3D Among them, the I region is the region where the thin film transistor is located, corresponding to Figure 2A-2D The section along the A-A' direction; the second area is the area where the gate pad structure is located, corresponding to Figure 2A-2D A section along the B-B' direction. The following will refer to Figure 2A-2D and Figure 3A-3D The production method of the present invention will be described.

[0024] refer to Figure 2A and Figure 3A First, a first conductive layer 101 , an insulating layer 102 , and a semiconductor layer 103 are sequentially formed on a transparent substrate 100 . The patterns of the semiconductor layer 103 , the insulating layer 102 and the first conductive layer 101 are further defined to...

Embodiment 2

[0032] The upper view of the manufacturing process of the second embodiment of the present invention and Figure 2A-2D marked the same. Figures 4A-4D A sectional view of the manufacturing process of the second embodiment of the present invention is shown. The biggest difference between the first embodiment and the second embodiment is that an insulating layer 202 is formed on the semiconductor layer 103 to protect the semiconductor layer 103 . In the second embodiment, the same names as those of the first embodiment use the same reference numerals.

[0033] refer to Figure 2A and Figure 4A On the substrate 100, a first conductive layer 101, a first insulating layer 102, a semiconductor layer 103 and a second insulating layer 202 are sequentially formed, and their patterns are defined to form a scanning line DL, a gate pad DLp and a gate DLg. In this embodiment, the second insulating layer 202 may be a silicon nitride layer.

[0034] refer to Figure 2B and Figure 4...

Embodiment 3

[0040] Figures 5A-5D It shows the top view of the manufacturing process of the third embodiment of the present invention. Figures 6A-6D A sectional view showing the manufacturing process of the third embodiment of the present invention. Figures 6A-6D Among them, the I region is the region where the thin film transistor is located, corresponding to Figures 5A-5D The cross-section along the A-A' direction; the area where the gate pad structure of the second region is located, corresponding to Figures 5A-5D A section along the B-B' direction. The following will refer to Figures 5A-5D and Figures 6A-6D A method of manufacturing a thin film transistor applied to a flat panel display according to the present invention will be described.

[0041] refer to Figure 5A and Figure 6A ,and Figure 5B and Figure 6B On the substrate 100 , the scan line DL, the gate pad DLp and the gate DLg are defined by the first conductive layer 101 , the first insulating layer 102 , the...

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Abstract

The manufacturing procedures includes following steps. (1) The first mask restricts the figure of the first metal layer / grid electrode insulation layer / non-silicon crystal layer. (2) The second mask restricts the formation of the passivation layer and the etching stopper. (3) The third mask restricts the formation of the source / drain electrode. (4) The fourth mask restricts the formation of the figure element electrode. The invented manufacturing process only needs to apply the said four masks so as to simplify the process for manufacturing the plain diaply of the thin film transistors.

Description

technical field [0001] The invention relates to a method for manufacturing a flat panel display, in particular to a method for manufacturing a thin film transistor liquid crystal display. Background technique [0002] Figure 1A to Figure 1D Shows the current manufacturing method of thin film transistors used in liquid crystal displays. refer to Figure 1A Firstly, a gate electrode 2 is defined and formed on a transparent substrate 1 , and then an insulating layer 3 is formed to cover the gate electrode 2 . Next, an amorphous silicon (amorphous silicon) layer 40 and a silicon nitride layer 50 are sequentially formed on the insulating layer 3 . refer to Figure 1B , limit etching the silicon nitride layer 50 to form an etching stopper (etching stopper) 5 . refer to Figure 1C A doped silicon layer 6 (for example, an amorphous silicon layer doped with n-type impurities) is formed on the etching stop layer 5 and the amorphous silicon layer 40 . ref...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/84G02F1/133G02F1/136
Inventor 赖宠文吴孟岳
Owner AU OPTRONICS CORP