Digital level shifter with reduced power dissipation and false transmission blocking

Abstract

A digital level shift circuit includes a level shifting device such as a high voltage MOS device and can also include feedback circuitry. The level shifting device is turned on to make an output transition, and the feedback circuitry obtains a feedback or acknowledge signal indicating that the transition was made. In response, the feedback circuitry turns off the level shifting device, which can reduce power dissipation. A digital level shift circuit that includes two n-channel devices and two p-channel devices can also include sense/prevent circuitry that senses when current greater than a threshold flows through both devices of one channel type and, in response, prevents output transitions from being made, which can avoid false transmissions due to rapid changes in offset voltage. Control circuitry in a digital level shift circuit can include both feedback circuitry and sense-prevent circuitry. In addition, the level shifting devices can be connected into a cross-acknowledge scheme in which none of the devices receives its acknowledge signal from the device to which it provides an acknowledge signal; this makes it possible to avoid a standoff between two devices. The control circuitry can also include, for each device, feedback detection circuitry to distinguish acknowledge signals, making it possible to restart a device that stops transmitting in response to a signal from another device that was not an acknowledge signal.

Description

technical field [0001] The present invention relates to a digital level shifter circuit having a circuit that reduces power consumption or blocks erroneous transmission due to rapid changes in offset voltage. Background technique [0002] Digital level shifting circuits typically place the low voltage input supply V DD The resulting digital signal is converted to a digital signal that can drift from a low input voltage to a rapidly changing relatively high voltage. The function of this digital level shifter is illustrated in FIGS. 1A and 1B , where the untranslated circuit 10 ( FIG. 1A ) is comparable to the translated circuit 12 ( FIG. 1B ). [0003] As shown in FIG. 1A, in an uninverted circuit 10, a voltage supply 20 provides a digital circuit 22 with a low voltage V DD . For example, V DD It can be any suitable fixed voltage between 1V and 15V. As shown in block 24, the digital circuit 22 then provides a voltage between 0V and V at its output (I / O). DD Switch betwe...

AI Technical Summary

Problems solved by technology

[0006] There are two main problems with integrated digital level shifters: power loss and OFFSET erroneous transmissions due to rapid changes in the

This solution has three main disadvantages: first, the duration of the transmission pulse is so long that it consumes a lot of power; second, even if the signal is good, the error filter introduces a delay; third, if the protective increment time is not enough large, errors may be transmitted on slow dv / dt

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