Bit line for memory assembly and method for making bit line contact window
A manufacturing method and contact window technology, applied in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve problems such as short circuits, achieve easy formation, improve the effects of easy short circuits, and low aspect ratio
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[0038] FIG. 3A to FIG. 3I are schematic cross-sectional views of the manufacturing process of the bit line and the bit line contact window of the memory device according to a preferred embodiment of the present invention.
[0039] Referring to FIG. 3A , firstly, a substrate 200 is provided, wherein the substrate 200 has a memory cell region 230 and a peripheral circuit region 240 . Next, several gate structures 208 are formed in the memory cell region 230, wherein each gate structure 208 has a gate dielectric layer 202, a gate conductive layer 204, and a top cover layer 206, and the gate structure 208 The sidewalls also include spacers 210 formed therein. In a preferred embodiment, the material of the gate dielectric layer 202 is, for example, silicon oxide, the material of the gate conductive layer 204 is, for example, polysilicon, the material of the top cover layer 206 is, for example, silicon nitride, and the material of the spacer 210 is, for example, is silicon nitride....
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