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Encapsulated pin structure for improved reliability of wafer

A technology of stitching and patterning, which is used in the assembly of printed circuits with electrical components, the formation of electrical connection of printed components, and the manufacture of printed circuits, which can solve problems such as complex structures.

Inactive Publication Date: 2007-05-16
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This complex structure requires the use of three masks

Method used

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  • Encapsulated pin structure for improved reliability of wafer
  • Encapsulated pin structure for improved reliability of wafer
  • Encapsulated pin structure for improved reliability of wafer

Examples

Experimental program
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Effect test

Embodiment Construction

[0025] Figure 1 shows the top region of an integrated circuit with unpatterned layers. At the bottom, box 200 represents an electronic structure such as an integrated circuit to be attached by contacts to be formed. Layer 30 is a dielectric layer such as polyimide that seals the structure to insulate the interconnects and block the penetration of moisture and other undesirable chemicals.

[0026] Box 35 schematically represents vias extending up through the polyimide from interconnects not shown. Contacts on top of the structure will make contact with these vias.

[0027] Layer 20 is a barrier and / or adhesion metallurgy layer. For example, use TiW, Ti, TaN and other materials known to those skilled in the art to block the penetration of contact materials, such as copper, and / or to improve the contact material and interconnect material (usually aluminum alloy) of adhesion.

[0028] Layer 10 is a seed layer that facilitates the deposition and plating of the material for the ...

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Abstract

A solder bump for bonding an electronic device to a substrate or another structure is formed by plating a high aspect ratio copper pin on a supporting structure, encapsulating the pin in a barrier material, plating a solder on the barrier material and then reflowing the solder.

Description

technical field [0001] The field of the invention is integrated circuit packaging, in particular flip-chip technology. Background technique [0002] Printed circuit boards (also referred to as printed wiring boards)—hereinafter simply referred to as “PCBs”—have become ubiquitous. A PCB is usually in the form of a dielectric substrate (such as a fiber-reinforced organic resin) coated with a conductor (such as copper) on one or both sides. The dielectric substrate has a predetermined pattern of apertures for connection to wiring and electrical devices, wherein the conductors are patterned to give predetermined circuit lines between the apertures so that the wiring and electrical devices are functionally interconnected. [0003] In the 1960s, IBM developed an interleaving technique to hardwire all interfaces, commonly referred to as "Controlled Folding Chip Connection" or simply "C4". According to this technique, the chip is connected to the electronics on the PCB through mat...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L23/48H01L21/44H05K3/34H05K3/40
CPCH01L2924/01015H01L2924/01082H01L2924/04953H01L2924/01079H05K3/3457H01L2924/14H01L2924/01327H01L2924/01322H01L2924/01033H01L2924/01006H01L2924/01029H01L2224/13099H01L2924/01022H01L2924/01078H01L2924/01073H05K3/4007H01L24/11H01L2924/014H01L2924/01013H01L2924/01024H01L24/03H01L24/05H01L24/13H01L2224/03622H01L2224/05001H01L2224/05026H01L2224/05568H01L2224/05647H01L2224/1147H01L2224/11849H01L2224/13076H01L2224/131H01L2924/00014H01L2224/05099
Inventor 郑天人戴维·E·艾施塔德乔纳森·H·格里菲思兰道夫·F·奈尔凯文·S·皮特拉卡罗杰·A·居昂
Owner INT BUSINESS MASCH CORP
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