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Method for improving n-type doping concentration of compound semiconductor under low growth temperature

A technology of doping concentration and compound, applied in semiconductor devices, semiconductor/solid-state device manufacturing, sustainable manufacturing/processing, etc., can solve problems such as time-consuming and manpower, increased flow of silane, waste, etc.

Inactive Publication Date: 2007-07-04
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the limitation of growth equipment, the flow rate of silane cannot be increased infinitely, and the increase of flow rate of silane will inevitably cause unnecessary waste
In addition, if an alternative dopant source is used, the growth equipment must be modified and calibrated, which consumes time and manpower.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0019] In a specific embodiment of the present invention, first, at a high growth temperature—such as 655°C, a layer of indium phosphide buffer layer is deposited on an indium phosphide substrate by MOCVD method; the thickness of the buffer layer is between 100nm and 300nm between.

[0020] The reaction chamber temperature was then lowered to below 600°C.

[0021] While keeping the flow rate of other reaction sources constant, reduce the flow rate of the group V reaction source phosphine passing into the reaction chamber, reduce the V / III ratio of the growth source passing into the reaction chamber to less than 100, and deposit n-type doping indium phosphide layer.

Embodiment 2

[0023] In another specific embodiment of the present invention, firstly, at a high growth temperature—such as 655° C., a layer of indium phosphide buffer layer is deposited on an indium phosphide substrate by MOCVD method; the thickness of the buffer layer is between 100 nm and 300 nm between.

[0024] The reaction chamber temperature was then lowered to below 600°C.

[0025] While keeping the flow rate of other reaction sources constant, reduce the flow rate of the group V reaction source arsine passing into the reaction chamber, so that the V / III ratio of the growth source passing into the reaction chamber is reduced to less than 100, and n-type doping is deposited. InGaAs layer.

[0026] The grown compound semiconductor layer is detected by electrochemical CV method, and the obtained results show that the n-type doping concentration greater than 1.0E19 is obtained in the indium phosphide and / or indium gallium arsenic thin films.

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Abstract

A method for improving the N type doping concentration in the compound semiconductor under low growing temperature, comprising: using the method of MOCVD to make the buffering layer grow on the substrate under high growing temperature; lowering the growing temperature of the reaction chamber; decreasing the ratio of the reaction resource V / III to the reaction chamber, keeping the flow capacity of the doping resource and other growing conditions and growing the N type doping compound semiconductor.

Description

technical field [0001] The invention relates to the field of semiconductor growth, in particular to a method for increasing the n-type doping concentration in indium gallium arsenic compound semiconductors. Background technique [0002] Due to its advantages in light absorption spectrum wavelength, circuit speed and power consumption, indium phosphide and its compound semiconductors have great application prospects in the field of long-wavelength optical fiber communication. The growth of high-quality indium phosphide and its compound semiconductors used in electrical devices (such as heterojunction bipolar transistors (HBT)) and optoelectronic devices that can be used in long-wavelength optical fiber communications is the basis for the application of this series of materials in this field. [0003] For example, in the growth process of the HBT device, in order to increase the doping concentration of the base region, a method of growing the entire device at low temperature c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/205H01L21/22H01L21/331H01L31/18
CPCY02P70/50
Inventor 江李林涛韦欣王国宏马骁宇
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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