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Chip conducting lug and re-distributed wire layer configuration

A conductive bump and redistribution technology, applied in circuits, electrical components, electrical solid devices, etc., can solve the problems of poor speed performance, high impedance, and difficulty in increasing the density of conductive bumps, reducing resistance value and increasing intersection. the effect of the probability of

Inactive Publication Date: 2002-07-10
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, not only the grounding or power supply conductive bumps require a long length of electrical wire, but the impedance will be large
And also due to uneven distribution, the speed performance is further deteriorated
In addition, the conductive bumps of the prior art described in the background of the invention also need to reserve a lead connection position, so the density of the conductive bumps will be difficult to increase

Method used

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  • Chip conducting lug and re-distributed wire layer configuration
  • Chip conducting lug and re-distributed wire layer configuration
  • Chip conducting lug and re-distributed wire layer configuration

Examples

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Embodiment Construction

[0045] The preferred embodiment of the present invention will be described in more detail with the help of the following figures in the following explanatory text:

[0046] The method provided by the invention, such as image 3 A schematic diagram of the first embodiment is shown. The common arrangement of conductive bumps arranged in an array at the core position of the flip-chip chip in the traditional method is changed to a row-to-row staggered arrangement. In addition, all signal conductive bumps have been moved to the periphery of the chip (not shown). The chip core 100 only has the voltage source conductive bump P and the ground conductive bump G.

[0047] still as image 3 , the conductive bumps listed in the marked row 120 and the conductive bumps listed in the left adjacent vertical row 110 and the right adjacent vertical row 130 are alternately arranged. Moreover, the voltage source conductive bumps P and the ground conductive bumps G in each vertical row are also...

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Abstract

The conducting lug and re-distributed wire layer configuration includes several power source connecting conducting lugs and earthing conducting lugs in honeycomb arrangement inside the chip, several power source, wires in 60 deg connected to the poer source connecting cnoducting lugs and several earthing wires in 60 deg connected to the earthing conducting lugs. The power source wires and the earthing wires crossed in the inner power bar and earthing bar have greater crossing probability. The conducting lugs are arranged in array mode, and the earthing and power source wires are in the re-distributed wire layer.

Description

technical field [0001] The invention relates to an integrated circuit packaging technology, in particular to the configuration of the redistribution wire layer designed in response to the core voltage source bump and the ground bump of the flip-chip chip. Background technique [0002] With the generational replacement of very large integrated circuit process technology, a single chip, the function is enhanced, and the level of packaging technology has to be greatly improved accordingly. Traditional large-scale integrated circuits or medium-sized integrated circuits use a lead frame to connect the input and output ends of the chip or contact pads, or wire contact pads, and then use ceramic or resin molding packaging methods, which are not enough for ultra-large integrated circuits. , not to mention VLSI. [0003] In the packaging method of connecting the contact pads with lead frames, in order to prevent the gold wires from being too long or the gold wires being shifted due ...

Claims

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Application Information

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IPC IPC(8): H01L21/60H01L23/50
CPCH01L2924/0002
Inventor 黄明坤
Owner VIA TECH INC
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