Chip conducting lug and re-distributed wire layer configuration

A conductive bump and redistribution technology, applied in circuits, electrical components, electrical solid devices, etc., can solve the problems of poor speed performance, high impedance, and difficulty in increasing the density of conductive bumps, reducing resistance value and increasing intersection. the effect of the probability of

Inactive Publication Date: 2002-07-10
VIA TECH INC
View PDF1 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, not only the grounding or power supply conductive bumps require a long length of electrical wire, but the impedance will be large
And also due to uneven distribution, the speed performance is further deterio

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Chip conducting lug and re-distributed wire layer configuration
  • Chip conducting lug and re-distributed wire layer configuration
  • Chip conducting lug and re-distributed wire layer configuration

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0045] The preferred embodiment of the present invention will be explained in more detail with the following graphics in the following description:

[0046] The method provided by the present invention, such as image 3 A schematic diagram of the first embodiment shown. The conventional array-type arrangement of conductive bumps at the core of a flip chip is changed to a row-to-row staggered arrangement. In addition, all signal conductive bumps have been moved to the periphery of the chip (not shown). The chip core 100 has only the voltage source conductive bumps P and the ground conductive bumps G only.

[0047] still as image 3 , the conductive bumps listed in the marked row 120 and the conductive bumps listed in the left adjacent column 110 and the right adjacent column 130 are arranged in a staggered arrangement, respectively. And the voltage source conductive bumps P and the ground conductive bumps G in each column are also presented in an alternate manner. In additi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The conducting lug and re-distributed wire layer configuration includes several power source connecting conducting lugs and earthing conducting lugs in honeycomb arrangement inside the chip, several power source, wires in 60 deg connected to the poer source connecting cnoducting lugs and several earthing wires in 60 deg connected to the earthing conducting lugs. The power source wires and the earthing wires crossed in the inner power bar and earthing bar have greater crossing probability. The conducting lugs are arranged in array mode, and the earthing and power source wires are in the re-distributed wire layer.

Description

technical field [0001] The invention relates to an integrated circuit packaging technology, in particular to the configuration of the redistribution wire layer designed in response to the core voltage source bump and the ground bump of the flip-chip chip. Background technique [0002] With the generational replacement of very large integrated circuit process technology, a single chip, the function is enhanced, and the level of packaging technology has to be greatly improved accordingly. Traditional large-scale integrated circuits or medium-sized integrated circuits use a lead frame to connect the input and output ends of the chip or contact pads, or wire contact pads, and then use ceramic or resin molding packaging methods, which are not enough for ultra-large integrated circuits. , not to mention VLSI. [0003] In the packaging method of connecting the contact pads with lead frames, in order to prevent the gold wires from being too long or the gold wires being shifted due ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L21/60H01L23/50
CPCH01L2924/0002
Inventor 黄明坤
Owner VIA TECH INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap