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Semiconductor memory

A technology of memory devices and semiconductors, used in static memory, digital memory information, information storage, etc.

Inactive Publication Date: 2003-05-07
NEC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is, a series of operations such as address determination, external address or update address selection, selected address decoding, and word line activation can only be performed step by step.

Method used

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  • Semiconductor memory
  • Semiconductor memory
  • Semiconductor memory

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment

[0062] figure 1 is a block diagram showing the structure of the semiconductor memory device of this embodiment, figure 2 yes means figure 1 A timing chart of the operation of each part in the shown semiconductor memory device. exist figure 1 In block ABn of , the external address Xn is a certain bit of an address for word line selection among addresses supplied from outside the semiconductor memory device.

[0063] Here, the present invention can also be applied to analog SRAM and MSRAM in addition to the above-mentioned general-purpose DRAM. Among them, the semiconductor memory devices of the latter two are compatible with SRAM, so there is no concept of row address and column address in the access address provided from outside the semiconductor memory device. Therefore, when these are used, in the semiconductor memory device of the present invention, an address supplied from the outside is theoretically divided into a row address and a column address.

[0064] Next,...

no. 2 Embodiment

[0099] In this embodiment, a specific example will be described in which the present invention is applied to a form in which the number of stages of decoders differs by a signal decoding system. Image 6 is a block diagram showing the structure of the semiconductor memory device of this embodiment, and figure 1 The same structural elements are marked with the same reference numerals.

[0100] In the figure, the external addresses ADDm and ADDn are some bits of the row address included in the external address. Furthermore, update address generating circuit 3 outputs update addresses RAm, Ran so as to correspond to these external addresses. Moreover, as far as the decoded signal Xn side is concerned, with figure 1 Similarly, an address buffer 1n, an update address buffer 4n, a first address decoder 2n, and a first update address decoder 5n are provided. One of the decoded signals generated by the two decoders is figure 1 The multiplexer 8n having the same structure as the...

no. 3 Embodiment

[0104] In each of the following embodiments after this embodiment, a case where the present invention is applied to a semiconductor memory device having a spare memory cell for defect recovery will be described. The present inventor applies the technical idea of ​​disposing the decoder before the multiplexer in the previous application ((Japanese) Japanese Patent Application No. 2000-63936; filed on March 8, 2002) to a device equipped with a preparatory storage unit. In the semiconductor memory device of the background art, it was found that the first embodiment and the second embodiment also cannot solve the problem.

[0105] For the semiconductor storage device of the background technology equipped with a spare storage unit, in the case of adopting the above-mentioned technical idea, it is considered that Figure 17 Between the shown external address EXT_ADD and the multiplexer 254, and between the update counter 253 and the multiplexer 254, a pre-decoder is configured respe...

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Abstract

A semiconductor memory the cycle time of which is shortened by accelerating the address access. A first address decoder (2) and a first refresh address decoder (5) decode an external address (Xn) fed from outside of the semiconductor memory and a refresh address (RXn) used for refresh in the semiconductor memory, respectively. A multiplexer (8) selects either a decode signal (XnDm) on the external address side or a decode signal (XnRm) on the refresh address side according to an external address transmission signal (EXTR) and a refresh address transmission signal (RFTR) so that a refresh and a Read / Write may be continuously performed in one memory cycle, and outputs the selected one as a decode signal (XnMm). A word driver (10) decodes the decode signals (XnMm, XpMq) selected by the multiplexer (8) and so forth so as to activate a word line (WLmq).

Description

technical field [0001] The present invention relates to a semiconductor storage device using a DRAM (Dynamic Random Access Memory) unit that needs to be updated to keep data as a storage unit, and in particular to a general-purpose SRAM (Static RAM) specification using a semiconductor storage device that uses a DRAM unit. (Asynchronous specification) Appropriate address access method for operation. Furthermore, the present invention relates to a semiconductor memory device applicable to a semiconductor memory device including a memory cell array that is accessed when there is no defect, and a spare memory cell array that replaces a defective memory cell on the memory cell array for defect relief. Address access method. Background technique [0002] A semiconductor memory device has been proposed which detects a transition of an external address supplied from the outside of the semiconductor memory device, performs an update of a memory cell indicating an update address whic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/403G11C11/401G11C11/406G11C11/407G11C11/408G11C29/04
CPCG11C11/406G11C11/4087G11C11/401
Inventor 高桥弘行稻叶秀雄园田正俊加藤义之中川敦
Owner NEC CORP
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