Digital PLL regulating crystal oscillator frequency and its regulation method

Abstract

A digital phase-locked ring to regulate frequency of crystal oscillator includes LIU, PD, DIV, DLF and OCXO, of which DLF consists of two first-in and first-out shift counters of FIFO, and FIFO2, accumulator ACC, mutiplying-dividing circuit and D/A converter. The method of realization for it is as follows: 1) phase error data sampling, 2) phase error data to be formed to be one-dimensional digital set {delta phi}m and to input them into FIFO, and FIFO2 as well as to get rid of a phase error data being sampled at the most early time, 3) accumulating phase error data delta phi and then to carryon averaging to calculate out the corresponding voltage controlled voltage value and 4) to regulate OCXO output frequency through D/A.

Description

technical field [0001] The present invention relates to the stabilization of electronic oscillators, in particular to a locked loop. Background technique [0002] With the wide application of various communication systems on public telecommunication networks, the scale of the network is getting larger and the network environment is becoming more and more complex, especially for various marginal networks such as wired access networks and wireless access networks. It is more complicated, for example, the transmission network relied on includes SDH (Synchronous Digital Hierarchy, synchronous digital system), PDH (Pseudo-synchronous Digital Hierarchy, quasi-synchronous digital system), digital microwave and even SDH / PDH hybrid network. On the other hand, the current transmission network is basically based on SDH. Although SDH has the advantages of unique broadband, strong self-healing ability, and powerful network management ability, the synchronization of it...

AI Technical Summary

Problems solved by technology

Therefore, the current network element equipment clock tolerance and smooth large jitter/drift

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