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Digital PLL regulating crystal oscillator frequency and its regulation method

A technology of crystal oscillator and digital phase-locked loop, applied in the direction of digital transmission system, automatic control of power, communication between multiple stations, etc., can solve the problem of network environment that cannot adapt to timing quality, clock tolerance and smooth large jitter/ Problems such as limited drifting ability, to achieve the effect of improving online survivability

Inactive Publication Date: 2003-07-30
ZTE CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the current network element equipment clock tolerance and smooth large jitter / drift capabilities are limited, and cannot adapt to the network environment with poor timing quality

Method used

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  • Digital PLL regulating crystal oscillator frequency and its regulation method
  • Digital PLL regulating crystal oscillator frequency and its regulation method
  • Digital PLL regulating crystal oscillator frequency and its regulation method

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Embodiment Construction

[0016] Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

[0017] The basic idea of ​​the sliding window DPLL design of the present invention is that the large integration time window slides forward with a smaller step value, that is, only a small part of data is refreshed in the integration time interval, and this part of data is together with most of the unrefreshed data. Sum and average. The hardware implementation method and the software implementation method are the sliding window DPLL hardware implementation circuit and software algorithm flow. The connection relationship and signal flow of each functional block of the sliding window DPLL.

[0018] figure 1 A sliding window digital phase-locked loop for use in a telecommunication network of the present invention is shown, which includes a LIU line interface unit, a PD phase detector, a DIV frequency divider, a DLF digital loop filter, and an ove...

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PUM

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Abstract

A digital phase-locked ring to regulate frequency of crystal oscillator includes LIU, PD, DIV, DLF and OCXO, of which DLF consists of two first-in and first-out shift counters of FIFO, and FIFO2, accumulator ACC, mutiplying-dividing circuit and D / A converter. The method of realization for it is as follows: 1) phase error data sampling, 2) phase error data to be formed to be one-dimensional digital set {delta phi}m and to input them into FIFO, and FIFO2 as well as to get rid of a phase error data being sampled at the most early time, 3) accumulating phase error data delta phi and then to carryon averaging to calculate out the corresponding voltage controlled voltage value and 4) to regulate OCXO output frequency through D / A.

Description

technical field [0001] The present invention relates to the stabilization of electronic oscillators, in particular to a locked loop. Background technique [0002] With the wide application of various communication systems on public telecommunication networks, the scale of the network is getting larger and the network environment is becoming more and more complex, especially for various marginal networks such as wired access networks and wireless access networks. It is more complicated, for example, the transmission network relied on includes SDH (Synchronous Digital Hierarchy, synchronous digital system), PDH (Pseudo-synchronous Digital Hierarchy, quasi-synchronous digital system), digital microwave and even SDH / PDH hybrid network. On the other hand, the current transmission network is basically based on SDH. Although SDH has the advantages of unique broadband, strong self-healing ability, and powerful network management ability, the synchronization of it...

Claims

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Application Information

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IPC IPC(8): H04L7/00H03L7/06H04B7/26
Inventor 宗柏青钟爽莉
Owner ZTE CORP
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