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Mfg method with regular embedded structure outline

A manufacturing method and construction technology, applied to the field of interconnection construction

Inactive Publication Date: 2003-10-22
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the dual damascene process faces the same issues as the single damascene process

Method used

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  • Mfg method with regular embedded structure outline
  • Mfg method with regular embedded structure outline
  • Mfg method with regular embedded structure outline

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Experimental program
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Embodiment Construction

[0019] The present invention provides a manufacturing method with a regular mosaic profile. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

[0020] refer to Figure 3A , is the first specific embodiment of the present invention. A semiconductor structure 30 is first provided having a conductive layer 31 formed thereon. The semiconductor structure 30 can be a semiconductor substrate formed of silicon or germanium or a conventional silicon-on-insulator structure. The semiconductor substrate 30 may further include one or more insulating layers, dielectric layers and / or conductive layers and one or more semiconductor devices formed thereon. The conductive layer 31 may include a metal layer, such as a copper metal layer, or other conductive material layers such as a doped silicon layer. The conductive layer 31 is usually an interconnection layer.

[0021] still refer to Figure 3A , a passivation layer 32 is formed ...

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Abstract

A process method for a regular mosaic structure profile includes: providing a basic material with a single inlay structure having a protecting layer orderly formed above basic material, a dielectric layer and a window hole penetrating the said dielectric layer and protection layer, and a wet etching program on the basic material utilizing deionized water, HCI and hydrofluoric acid etching solution making the etching option ratio between layers to be 1:1.

Description

(1) Technical field [0001] The present invention relates to an interconnect structure, and more particularly to a damascene structure with improved profile. (2) Background technology [0002] For semiconductor processes below 0.25 micron critical dimension, it is necessary to use a so-called damascene technique to fabricate interconnections due to the difficulty in fabricating interconnections using traditional aluminum metal deposition and etching processes. In addition, considering the performance of semiconductor devices below this critical dimension, metals with lower resistance values, such as copper metals, are often used. Low-resistance metals cannot be etched for interconnect patterns by reactive ion etching. Therefore, the use of copper as the interconnection increases the demand for the damascene process. [0003] In addition to using low-resistance metals such as copper, copper conductors are also combined with low-k dielectric layers (k value less than 4) to im...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/311H01L21/768
CPCH01L21/76807H01L21/76802H01L21/31111
Inventor 洪任谷孙国维
Owner UNITED MICROELECTRONICS CORP