Mfg method with regular embedded structure outline
A manufacturing method and construction technology, applied to the field of interconnection construction
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[0019] The present invention provides a manufacturing method with a regular mosaic profile. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
[0020] refer to Figure 3A , is the first specific embodiment of the present invention. A semiconductor structure 30 is first provided having a conductive layer 31 formed thereon. The semiconductor structure 30 can be a semiconductor substrate formed of silicon or germanium or a conventional silicon-on-insulator structure. The semiconductor substrate 30 may further include one or more insulating layers, dielectric layers and / or conductive layers and one or more semiconductor devices formed thereon. The conductive layer 31 may include a metal layer, such as a copper metal layer, or other conductive material layers such as a doped silicon layer. The conductive layer 31 is usually an interconnection layer.
[0021] still refer to Figure 3A , a passivation layer 32 is formed ...
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Abstract
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