Phase transformation memory and manufacturing method thereof

Abstract

First, an N+polycrystal layer and an N- polycrystal layer are formed on a semiconductor substrate. The first shallow-channel isolation structure is formed in the N+ layer in order to isolate the prearranged character line region; and the second shallow-channel isolation structure is formed in the N- layer in order to isolate the prearranged P+ adulteration region. Next, the defined insulation layer is formed. N+ adulterating is carried out for the part of N- polycrystal layer in order to connect N+ adulteration region in N+ polycrystal layer. P+ is adulterated in the N+ polycrystal layer so as to form a P+ adulteration region. The, the contact plug across the insulation layer is formed on the N+ adulteration region and the P+ adulteration region respetively. Finally, an upper electrode, a phase change layer and a lower electrode are formed on the contact plug being as an electrod.

Description

technical field

[0001] The invention relates to a memory, in particular to a phase-change memory and a manufacturing method thereof. Background technique

[0002] figure 1 To show the traditional phase change memory structure. The phase change memory structure includes a semiconductor substrate 10, an N+ doped layer 12 formed on the semiconductor substrate 10, an N-doped layer 14 formed on the N+ doped layer 12, and an N+ doped region 16 formed on the In the N-doped layer 14, a P+ doped region 18 is formed in the N-doped layer 14, and an insulating layer 20 is formed on the semiconductor substrate 10, and the insulating layer 20 can be an oxide layer. The contact plug 22 includes a barrier layer 24 and a metal layer 26 . The electrodes 28 are respectively formed on the contact plugs 22 , and the electrodes 28 have an upper electrode 34 , a phase change layer 32 and a lower electrode 30 .

[0003] The thickness and doping concentration of the N+ doped region and the N− do...

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