Single-output feedback-free sequential test response compression circuit

Abstract

The present invention relates to a test response compressor in design of chip testability, and provides a single-output sequential comprssion circuit: quotient-compressor. Said compression circuit includes two portions: (1) response diffusion network and (2). quotient-shifting register chain. Said invention also provides three rules must be met for designing diffusion matrix correspondent to the response diffusion network, and its compression rate is high, and its testing time can be reduced, and it has no erroneous judgement.

Description

Technical field [0001] The invention relates to the technical field of testability of integrated circuit chips, in particular to a single-output non-feedback timing test response compression circuit in a chip full scan design. Background technique [0002] With the development of technology, especially with the development of system-level chips, more and more logic units (such as microprocessors, memories, DSPs, I / O controllers) are integrated on a single chip, and their functions are becoming more and more complex. It brings many new challenges to the test. These challenges mainly include: 1) The test frequency of the test equipment cannot keep up with the increase in chip frequency; 2) The test time is too long, resulting in a significant increase in test costs; 3) The memory capacity of the test equipment is insufficient; 4) The chip can be used as a test lead for a full scan design. Insufficient feet. A feasible solution to the shortage of test pins is to compress the test re...

AI Technical Summary

Problems solved by technology

[0002] With the development of technology, especially with the development of system-level chips, more and more logic units (such as microprocessors, memories, DSPs, I / O controllers) are integrated on a single chip, and their functions are becoming more and more complex. Brings many new challenges to testing

These challenges mainly include: 1) The test frequency of the test equipment cannot keep up with the increase in chip frequency 2) The test time is too long, resulting in a substantial increase in test cost 3) The memory capacity of the test equipment is insufficient 4) The chip can be used as a test guide for full-scan designs Insufficient feet

2) The response may contain many uncertain bits

3) It must be possible to provide a simple method to collect complete diagnostic information, and this diagnosis must be without assumptions

A disadvantage of combinational circuits is that they have low compression ratios and do not provide a complete targeting solution, and their diagnosis must be based on assumptions that cannot be guaranteed

Uncertain bits cannot be completely eliminated in large-scale SOC design

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