The invention is applied to compress the test response. Figure 2 depicts the full scan design framework with quotient-compressor. It can be seen from the figure that the response compressor is designed on the output of the scan chain. Compress the output of multiple scan chains into one output, and output to the test equipment through a scan output pin for comparison. Therefore, from the perspective of the entire design process, the design of the response compressor and the design of the scan chain are basically independent of each other. Therefore, there is no need to modify the design flow of the original chip in response to the insertion of the compressor, nor does it need to modify the testability design flow of the original chip.
 Figure 3 lists the applicator-compressor design flow for testability. It can be seen that the testability design process for an applier-compressor can be divided into the following steps:
 1) Comprehensive, scan chain design. At this step, you need to plan the pins that can be used for scan chain design. Because the quotient-compressor has a single output, only one output pin is reserved for the output of the compression circuit, and other pins can be used for input. Among these inputs, only one pin needs to be reserved for qmask, and the others can be used as the input of the scan chain. Therefore, we can design up to M-2 scan chains for the available scan pins M. Plan the number of scan chain designs in this step, and insert scan chains in the synthesis process;
 2) Design, insert quotient-compressor. When the scan chain is designed, a diffusion matrix that meets the conditions is automatically generated according to the three design rules proposed in the present invention. Then use a comprehensive tool to automatically generate a diffusion network. A complete quotient-compressor can be obtained by connecting the diffusion network and the quotient-register chain. Then it is included as a separate design module into the overall design. Then conduct a design rule check on the overall design to check whether there is too much delay or other electrical deficiencies.
 3) Use ATPG tool to generate test vector for scan chain design, and convert it into a parallel structure, adjust the fault simulator to get the response result of the beat. And output to a quotient-compressor software simulator. The software simulator can quickly simulate the compressed output results according to the specific configuration. And record it in the vector file.
 4) Combine the scan chain input generated by the ATPG tool and the result of the quotient-compressor software simulation into a test vector, and add the qmask control signal. The output is used as the final test vector. That is, the vector generated by the ATPG tool and the result obtained by the compressor simulator are combined to obtain the final test vector.
 In this process, automatically generating the quotient-compressor diffusion matrix is a key issue. In the algorithm of automatically generating the diffusion matrix, we have to consider the influence of the designed XOR tree on the delay. For the diffusion matrix conforming to the above three design rules, due to the difference of the values of each row, the delay of the generated XOR tree on the critical path may be very different. If the XOR gates on each input path of the designed XOR tree are more evenly distributed, the overall performance can be optimized.
 In the present invention, since the quotient-compressor is a single-output compression circuit, it has the characteristic of high compression rate. The full scan design of the applier-compressor can increase the scan chain by 2 times, shorten the length of the scan chain, and reduce the test time. At the same time, a special design is made for the fault models that are easy to appear in the scan test to ensure that there is no misjudgment. The quotient-compressor is also capable of handling uncertain bits. If some diagnostic operations are inserted, the quotient-compressor can provide the ability to completely collect the output information of the scan chain.