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Single-output feedback-free sequential test response compression circuit

A circuit and compressor technology, which is applied in the field of single-output non-feedback timing test response compression circuit, which can solve the problems of long test time, low compression rate, and inability to guarantee

Active Publication Date: 2003-12-10
INST OF COMPUTING TECHNOLOGY - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] With the development of technology, especially with the development of system-level chips, more and more logic units (such as microprocessors, memories, DSPs, I / O controllers) are integrated on a single chip, and their functions are becoming more and more complex. Brings many new challenges to testing
These challenges mainly include: 1) The test frequency of the test equipment cannot keep up with the increase in chip frequency 2) The test time is too long, resulting in a substantial increase in test cost 3) The memory capacity of the test equipment is insufficient 4) The chip can be used as a test guide for full-scan designs Insufficient feet
2) The response may contain many uncertain bits
3) It must be possible to provide a simple method to collect complete diagnostic information, and this diagnosis must be without assumptions
A disadvantage of combinational circuits is that they have low compression ratios and do not provide a complete targeting solution, and their diagnosis must be based on assumptions that cannot be guaranteed
Uncertain bits cannot be completely eliminated in large-scale SOC design

Method used

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  • Single-output feedback-free sequential test response compression circuit
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  • Single-output feedback-free sequential test response compression circuit

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Embodiment Construction

[0051] The invention is applied to compress the test response. Figure 2 depicts the full scan design framework with quotient-compressor. It can be seen from the figure that the response compressor is designed on the output of the scan chain. Compress the output of multiple scan chains into one output, and output to the test equipment through a scan output pin for comparison. Therefore, from the perspective of the entire design process, the design of the response compressor and the design of the scan chain are basically independent of each other. Therefore, there is no need to modify the design flow of the original chip in response to the insertion of the compressor, nor does it need to modify the testability design flow of the original chip.

[0052] Figure 3 lists the applicator-compressor design flow for testability. It can be seen that the testability design process for an applier-compressor can be divided into the following steps:

[0053] 1) Comprehensive, scan chain design. ...

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Abstract

The present invention relates to a test response compressor in design of chip testability, and provides a single-output sequential comprssion circuit: quotient-compressor. Said compression circuit includes two portions: (1) response diffusion network and (2). quotient-shifting register chain. Said invention also provides three rules must be met for designing diffusion matrix correspondent to the response diffusion network, and its compression rate is high, and its testing time can be reduced, and it has no erroneous judgement.

Description

Technical field [0001] The invention relates to the technical field of testability of integrated circuit chips, in particular to a single-output non-feedback timing test response compression circuit in a chip full scan design. Background technique [0002] With the development of technology, especially with the development of system-level chips, more and more logic units (such as microprocessors, memories, DSPs, I / O controllers) are integrated on a single chip, and their functions are becoming more and more complex. It brings many new challenges to the test. These challenges mainly include: 1) The test frequency of the test equipment cannot keep up with the increase in chip frequency; 2) The test time is too long, resulting in a significant increase in test costs; 3) The memory capacity of the test equipment is insufficient; 4) The chip can be used as a test lead for a full scan design. Insufficient feet. A feasible solution to the shortage of test pins is to compress the test re...

Claims

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Application Information

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IPC IPC(8): G01R31/28G06F7/52H01L23/58
Inventor 韩银和李晓维
Owner INST OF COMPUTING TECHNOLOGY - CHINESE ACAD OF SCI
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