Loading method for ensuring to load programmable part reliably

Abstract

The invention relates to watch dog / voltage monitoring technique and application method of FPGA. The method includes following steps. (1) After power up, voltage-monitoring chip starts work to monitor operating voltage Vd first. (2) Whether Vd is larger than threshold Vpfi of the chip is determined in order to meet condition for FPGA to start configuration. (3) If Vd>Vpfi, then the control signal PFO output from the chip is high, configuration procedure is started by FPGA; if Vd is less than or equal or Vpfi, the loading configuration procedure is prohibited. A divider circuit is added in front of the voltage-monitoring chip. Resistance potential-divider network A1 obtains voltage division, which is also as input of PFI, of voltage Vcc to be monitored. Sharing function of voltage-monitoring circuit detects the time when single board / device enters into normal state in order to guarantee that FPGA completes loading under correct state.

Description

technical field [0001] The invention relates to a method for realizing delayed loading of FPGA by using a watchdog / voltage monitoring circuit, and mainly relates to a watchdog / voltage monitoring technology in the field of electronic technology and an application method of FPGA. Background technique: [0002] In FPGA applications, an additional PROM is usually required to store the data required for FPGA loading. This loading process is usually completed automatically when the board or device is powered on. Because this loading process is executed after judging the power supply voltage through a certain pin of the FPGA chip, and the FPGA is a pure digital chip, it cannot detect the analog quantity. In other words, as long as the voltage of the detection pin is judged to be high , the FPGA loading process begins, and for TTL signals, a voltage exceeding 1.7V will be judged as a high level. Under such conditions, it may happen that the FPGA starts to load before the power supp...

AI Technical Summary

Problems solved by technology

One is to use a fast-start power supply, and then use the delay of the FPGA itself. This solution requires a very short time for the power supply to rise from 0V to 3.3V, but it brings two problems at the same time. One is to limit the choice of power supply. The second is the negative impact of fast power-on on the life and reliability of the chip

The second solution is to add a capacitor to the detection pin of the FPGA. This solution can avoid the defects of the previous solution. However, due to the energy storage effect of the capacitor, when the device is powered on quickly after power-off, it may also cause damage to the device when it fails to load. chip damage

In this way, there is a congenital deficiency in reliability

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