Self-testing method and apparatus for synchronous dynamic random memory

Abstract

A method and apparatus for performing self-test to synchronized dynamic random access memory, wherein the method comprises, starting self-test to synchronized dynamic random access memory SDRAM, switching the system to self-test mode, the CPU writing data to the first pair port RAM of the self-test module, the arbitration module reading data from the first pair port RAM and writing into SDRAM, the arbitration module reading back data from SDRAM and writing into the second pair port RAM of the self-test module, the CPU comparing the write-in and read-out data for determining whether SDRAM is operating normally. The invention increases the system reliability and maintainability.

Description

technical field [0001] The invention relates to a method for buffering data input from a media access control MAC layer by a synchronous dynamic random access memory SDRAM (Synchorous DRAM) to achieve reliable flow control in the process of Ethernet transparent transmission of a synchronous digital system SDH. Background technique [0002] In the process of realizing Ethernet transparent transmission SDH, SDRAM is required to cache the data input from the MAC layer to realize flow control. SDRAM is a dynamic random access memory DRAM that completes data reading and writing under the control of an external synchronous clock. Like ordinary DRAM, it needs periodic refreshing operation, and the row address must be given before the access, and then the column address must be given. However, the input signals of SDRAM are latched with the rising edge of the system clock, so that the device can operate completely synchronously with the system clock. It embeds a synchronous contro...

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Problems solved by technology

[0003] Due to various harsh environments that may be encountered in actual working conditions, it may cause failure of the SDRAM or the read-write arbitration module and SDRAM controller that control the SDRAM. Once this happens, the entire flow control unit (referred to as : flow control unit) data path paralysis

[0004] In addition, the SDRAM part belongs to the 100M clock domain in the system, and the timing is difficult to meet the requirements, which is a weak link in the system. Therefore, it needs to be remedied in some way

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