Upper thermal field used for six inch and eight inch adulterated phosphorus vertical pulling silicon mono crystal manufacture

A technology of Czochralski silicon and single crystal, applied in the direction of single crystal growth, single crystal growth, crystal growth, etc., can solve the problem of increasing the temperature gradient G at the solid-liquid interface, and cannot grow six-inch and eight-inch heavy phosphorus-doped Czochralski Silicon single crystal and other problems, to achieve the effect of enhancing the purging effect, strengthening the cooling effect, and increasing the temperature gradient

Active Publication Date: 2004-12-22
金瑞泓科技(衢州)有限公司
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Problems solved by technology

[0018] The invention enhances the purging effect of the air flow on the surface of the melt, and the tiny particles produced by volatilization are effectively blown away from the upper part of the melt; the new thermal field structure strengthens the cooling effect on the single crystal, thereby increasing the temperature at the solid-liquid interface Gradient G, using the new thermal field of the present invention solves the difficult problem that six-inch and eight-inch heavily phosphorus-doped Czochralski silicon single crystals cannot be grown in ordinary standard thermal fields, making six-inch and eight-inch heavily phosphorus-doped Czochralski silicon single crystals The growth becomes as easy as ordinary high-resistivity Czochralski silicon single crystal

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  • Upper thermal field used for six inch and eight inch adulterated phosphorus vertical pulling silicon mono crystal manufacture
  • Upper thermal field used for six inch and eight inch adulterated phosphorus vertical pulling silicon mono crystal manufacture
  • Upper thermal field used for six inch and eight inch adulterated phosphorus vertical pulling silicon mono crystal manufacture

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[0026] The present invention (see Figure 4 The part with hatching in ) and ordinary thermal field ( figure 2 ) The main difference is that the new thermal field has increased the upper part of the thermal field composed of upper cover plate 18, air guide cover 19, and support cylinder 17, and these parts are all made of high-purity graphite. The support cylinder 17 and the upper cover plate 18 mainly play the role of support and heat preservation, and the air guide cover 19 mainly plays the role of heat preservation and adjustment of the upper flow field of the melt.

[0027] Heat preservation cover 19 is upper and lower two hollow truncated cone connectors (see Figure 5 ), the bottom angle A of the upper truncated cone is 30 to 40°, the bottom angle B of the lower truncated cone is 60-70°; the diameter of the bottom of the upper truncated cone is D 1 And the selection of the bottom angle A of the upper conical truncated must ensure that the diameter control probe 14 will...

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Abstract

A top heat field for preparing 6-inch and 8-inch heavyly doped monosilicon by straight pulling up is composed of an insulating cover consisting of the upper and lower hollow trancated cones, and an upper cover plate fixed to the top of said insulating cover and put on a supporting pipe. It can enhance the scavenge action of the airflow on the surface of molten body for removing the fine particles from the surface.

Description

technical field [0001] The invention relates to an upper thermal field for manufacturing six-inch and eight-inch heavily phosphorus-doped Czochralski silicon single crystals. Background technique [0002] Heavily doped Czochralski silicon single crystals are used to produce epitaxial substrates. Growing a high-resistivity epitaxial layer on a low-resistivity heavily doped substrate can solve the contradiction between the high breakdown voltage of bipolar transistors (requiring the use of high-resistivity silicon wafers) and low collector resistance, and can reduce bipolar transistors. The power consumption of the pole transistor is improved, and the response effect of its high-frequency signal is improved. Growing a high-resistivity silicon epitaxial layer on a low-resistivity heavily doped silicon substrate can also be used to solve the latch-up problem of CMOS components. [0003] Device manufacturing requires low substrate resistivity, but the ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): C30B15/14C30B29/06
Inventor 田达晰马向阳林必清李晓军李立本
Owner 金瑞泓科技(衢州)有限公司
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