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Electro-static discharge protection circuit and method for making the same

A technology of electrostatic discharge protection and electrostatic discharge, which is used in circuits, electrical components, electrical solid devices, etc.

Inactive Publication Date: 2005-08-03
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when Vds becomes high enough, cumulative breakdown occurs, and the FET then conducts

Method used

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  • Electro-static discharge protection circuit and method for making the same
  • Electro-static discharge protection circuit and method for making the same
  • Electro-static discharge protection circuit and method for making the same

Examples

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Embodiment Construction

[0022] Figure 1 is a cross-sectional view illustrating an array of memory cells, as provided in a dynamic random access memory (DRAM) and as described in commonly assigned published US Patent Application No. US 2002 / 0196651 Al. And the memory cell array is described as background of the invention, it is not considered as prior art.

[0023] The ESD circuits described in the following embodiments are formed by some of the same steps as the methods used to form the memory cell arrays described herein. The illustrated section of the section is indicated in the direction of the bit line 16 . As shown in FIG. 1, a storage capacitor 22 is formed in each deep trench 20 with a node electrode 21 forming a plate, a node dielectric 29, and a doped buried pattern surrounding the substrate. Plate area 31 (which is the other plate of the capacitor 22). Deep trench 20 also includes trench collar oxide 30 and trench top oxide 32, which prevent parasitic leakage currents, highly doped buried...

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PUM

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Abstract

As disclosed herein, an electrostatic discharge (ESD) protection circuit is provided for an integrated circuit including a semiconductor substrate. The ESD protection circuit includes a plurality of active devices formed in the semiconductor substrate, the active devices being formed by a process including a plurality of steps carried out to form, at the same time, a plurality of active devices having a function other than ESD protection. For example, the ESD circuit may include an array of vertical transistors formed according to a process including many of the steps used to form, at the same time, vertical transistors of a DRAM array. Also disclosed is the formation of an ESD circuit in an 'unusable' area of a semiconductor chip, such as under a bond pad, land or under bump metallization of the chip.

Description

technical field [0001] The invention relates to an electrostatic discharge protection circuit and a manufacturing method thereof. Background technique [0002] Electrostatic discharge protection circuits (hereinafter referred to as "ESD circuits") are provided in many semiconductor integrated circuits (hereinafter referred to as "chips") to help prevent sudden failure due to electrostatic discharge across the chip via its external terminals. Although once common, such failures are far less common today where ESD circuits are widely used. [0003] ESD circuits occupy a considerable chip area in preparation for reducing the large amount of current that occurs during electrostatic discharge. Static charges can have voltages measured at voltage thresholds in excess of 100 times and sometimes in excess of 1000 times that present during normal operation. Current is known to flow through a single external terminal of a packaged chip if within such range For the current to be hand...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/60H01L23/62H01L27/00H01L27/02H01L27/085H01L29/76H01L29/94H01L31/119H10B12/00
CPCH01L27/0255H01L27/10897H01L27/10841H10B12/395H10B12/50
Inventor G·麦内尔
Owner INFINEON TECH AG