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Method for mfg wired substrate and method for mfg electronic apparatus

A wiring substrate and substrate technology, which is applied in the fields of printed circuit manufacturing, electrical component assembly printed circuit, semiconductor/solid-state device manufacturing, etc., can solve the problem of multiple manufacturing steps, resource and material consumption, and dependence on photosensitive resist for wiring dimensional accuracy Layer definition and other issues, to achieve low cost, reduce material waste, and reduce waste

Inactive Publication Date: 2005-08-10
SEIKO EPSON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] According to these methods, there is a problem of resource and material consumption in the final removal of the photoresist layer and in the removal of part of the metal layer in the subtractive method
In addition, since the formation and removal steps of the photoresist layer are required, there is a problem that there are many manufacturing steps.
Furthermore, the dimensional accuracy of the wiring depends on the definition of the photoresist layer, so there is a certain limit for forming higher-precision wiring.

Method used

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  • Method for mfg wired substrate and method for mfg electronic apparatus
  • Method for mfg wired substrate and method for mfg electronic apparatus
  • Method for mfg wired substrate and method for mfg electronic apparatus

Examples

Experimental program
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no. 1 example

[0054] figure 1 (A)~ Figure 5 (B) is an explanatory diagram of a method of manufacturing a wiring substrate according to the first embodiment of the present invention. In this embodiment, an electroless gold plating process is applied to manufacture the wiring substrate.

[0055] first case

[0056] figure 1 (A)~ Figure 4 (B) is an explanatory diagram of the first example of this embodiment. figure 1 (A)~ figure 2 (B) is an explanatory diagram of each step of the electroless gold plating process, image 3 (A)~ Figure 4 (B) is a schematic diagram of the substrate in various steps of the electroless gold plating process.

[0057] The substrate (thin plate) 10 may be a flexible substrate. As the flexible substrate, an FPC (Flexible Printed Circuit), a COF (Chip On Film) substrate, or a TAB (Tape Automated Bonding) substrate can be used. The substrate 10 may be formed of an organic material such as resin. As the substrate 10, a polyimide substrate or a polyester subst...

no. 2 example

[0080] Figure 6 (A)~ Figure 10 (B) is an explanatory diagram of a method of manufacturing a wiring substrate according to the second embodiment of the present invention. In this embodiment, the surfactant is patterned by using a liquid jet method.

[0081] first case

[0082] Figure 6 (A)~ Figure 7 (B) is an explanatory diagram of each step of the electroless gold plating process. Figure 8 (A)~ Figure 9 (B) is a schematic diagram of the substrate in each step of the electroless gold plating process.

[0083] Such as Figure 8 As shown in (A), as the substrate 10, the surface potential thereof is set to a negative potential in advance. Such as Figure 6 As shown in (A), alkaline cleaning can be performed by immersing the substrate 10 in an alkaline solution (for example, an inorganic alkaline solution) 62 . Thus, if Figure 8 As shown in (B), the uneven potential on the surface of the first region 12 and the second region 14 of the substrate 10 can be changed t...

no. 3 example

[0095] Figure 11 is a schematic diagram for explaining a method of manufacturing an electronic device according to a third embodiment of the present invention, specifically showing an example of an electronic device having a wiring substrate.

[0096] A metal layer having a predetermined pattern shape is formed on the wiring substrate 1 (in Figure 11 omitted). A semiconductor chip 80 having an integrated circuit can be mounted (for example, flip-chip) on the wiring substrate 1 . The semiconductor chip 80 (integrated circuit) is electrically connected to the metal layer. In this way, the semiconductor device 3 including the semiconductor chip 80 and the wiring substrate 1 can be manufactured. Then, wiring substrate 1 (or semiconductor device 3 ) is electrically connected to circuit board 82 . Thus, an electronic device can be manufactured. In addition, the wiring substrate 1 can also be as Figure 11 bend as indicated by the arrow.

[0097] When the circuit board 82 is...

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Abstract

A method for manufacturing a wiring substrate includes the steps of (a) providing a surface-active agent in first and second areas of a substrate, (b) irradiating a vacuum ultraviolet radiation to the second area of the substrate to thereby break down an interatomic bond in the second area of the substrate, (c) washing the substrate to thereby remove a portion of the surface-active agent in the second area, (d) providing a catalyst on an area of the surface-active agent remaining in the first area, and (e) depositing a metal layer to the catalyst to thereby form a wiring composed of the metal layer along the first area.

Description

technical field [0001] The present invention relates to a method of manufacturing a wiring substrate and a method of manufacturing an electronic device. Background technique [0002] As well known, methods for forming wiring on a flexible substrate include a subtractive method and an additive method. In the subtractive method, a metal layer is formed on the entire surface of the flexible substrate, a photosensitive resist layer is patterned on the metal layer, and the photosensitive resist layer is isolated to etch the metal layer. In the additive method, a photosensitive resist layer is patterned on a flexible substrate, and a metal layer is deposited by a gold plating process on the opening from the photosensitive resist layer. [0003] According to these methods, resource and material consumption problems arise both in the final removal of the photoresist layer and in the removal of parts of the metal layer in the subtractive method. In addition, since steps of forming ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): C23C18/20C23C18/16C23C18/28H01L21/48H01L21/60H01L23/12H01L23/498H05K1/03H05K3/18H05K3/32
CPCH05K2203/013C23C18/285C23C18/204C23C18/1608H05K3/182C23C18/2086H01L21/4846C23C18/30H05K2203/122C23C18/1612H01L23/4985C23C18/28H05K3/185H01L2924/0002Y10T29/49162H01L2924/00
Inventor 木村里至降旗荣道丸茂实
Owner SEIKO EPSON CORP