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Reduced chip testing scheme at wafer level

A chip, untested technology, applied in the direction of electronic circuit testing, semiconductor/solid-state device testing/measurement, measuring electricity, etc., can solve the problem of multiple waste products

Inactive Publication Date: 2005-10-12
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

While the yield loss due to these errors may be low, it is repeated on every wafer which ultimately results in a lot of rejects

Method used

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  • Reduced chip testing scheme at wafer level
  • Reduced chip testing scheme at wafer level
  • Reduced chip testing scheme at wafer level

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Embodiment Construction

[0066] The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and not restrictive. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. For example, in figure 1 The dimensions of chip 4 and probe tip 8 are exaggerated.

[0067] Where the term "comprising" is used in the present description and claims, it does not exclude other elements or steps. When an indefinite or definite article (eg "a," "the") is used to refer to a singular noun, a plurality of that noun is included unless something else is stated otherwise.

[0068] Reference will be made primarily to chips on a wafer, but the invention relates to the testing of any semiconductor device produced at the wafer level, including but not limited to ICs, diodes, transistors. A component may...

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PUM

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Abstract

The present invention relates to production testing of semiconductor devices, more specifically to production testing of such devices at wafer level.A method according to the present invention comprises the steps of generating (20) quality test-data at a limited number of semiconductor devices on the wafer, deciding (24) based on the generated quality test-data whether other semiconductor devices on the wafer are to be tested, and based on the result of the deciding step, testing (28) or not testing (26) the other semiconductor devices on the wafer.A corresponding wafer prober is also described.

Description

technical field [0001] The present invention relates to the testing of semiconductor devices, especially active devices such as chips, and in particular to the production testing of such devices at wafer level, ie before the wafer is cut or diced into individual chips and assemblies of these chips. Background technique [0002] The manufacturing phase of an integrated circuit can be divided into two steps. The first step in wafer fabrication is the intricate process of making silicon chips (also called dies). The second assembly step is a highly precise and automated process of packaging the die. These two stages are commonly referred to as "front end" and "back end" respectively. Production test is testing during semiconductor device manufacturing, which is distinguished from chip testing that occurs during design or production support, which is often referred to as engineering testing. [0003] At the beginning of the assembly phase, the silicon chips are gathered on a ...

Claims

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Application Information

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IPC IPC(8): H01L21/66G01R31/28
CPCG01R31/2831
Inventor C·O·西科P·C·N·谢尔瓦特
Owner NXP BV