Method for realizing to reset main device in 12C bus and resetting apparatus and equipment thereof

A technology of reset device and implementation method, which is applied in the direction of instruments, electrical digital data processing, etc., can solve the problem of I2C bus being locked, and achieve the effect of low hardware cost and improved adaptability

Inactive Publication Date: 2006-03-01
ZTE CORP
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  • Abstract
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Problems solved by technology

[0019] However, there are often many devices connected to the I2C bus in computer communication equipment, and the I2C master device (usually the CPU) does not necessarily have a control register to solve the I2C bus lock state. At the same t

Method used

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  • Method for realizing to reset main device in 12C bus and resetting apparatus and equipment thereof
  • Method for realizing to reset main device in 12C bus and resetting apparatus and equipment thereof

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[0033] The implementation of the technical solution will be described in further detail below in conjunction with the accompanying drawings:

[0034] figure 1 Shown is a structural block diagram of the reset device of the master device in the I2C bus of this embodiment. As shown in the figure, the device includes a master device 101 on the I2C bus, a reset device 102 of the master device, and a slave device 103 of the I2C bus. In this embodiment, the main device 101 is a CPU processor. Generally, there are multiple slave devices 103 on the I2C bus, and only one of them is shown in the figure.

[0035] The reset device 102 is implemented by a programmable logic device (PLD) in this embodiment, and this device is a functional module formed by the internal logic circuit of the PLD. In practical applications, in order to form a modularization and adapt to PLD devices of multiple manufacturers, this functional module is generally implemented by the hardware description language Veril...

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Abstract

The method for implementing main device reset in 12C bus includes the following steps: real-time detecting 12C bus state, when the external signal for requiring main device to reset is received, judging current 12C bus state, if it is idle, immediately implementing main device reset, if it has 12C bus operation cycle, after said operation cycle is completed, making main device reset. Said reset device includes monitoring portion and reset control portion. Said invention also provides the concrete action of every portion.

Description

technical field [0001] The invention relates to the situation of using the I2C bus in the communication equipment, especially the method and device for realizing the reset of the master device in the I2C bus structure. Background technique [0002] The I2C bus (Inter-IC BUS or IIC BUS, inter-integrated circuit interconnection bus) is a set of serial buses developed by Philips (PHILIPS) for connecting microcontrollers and their peripherals. The I2C bus has two signal lines: a clock line SCL and a bidirectional data line SDA. The clock lines SCL of all devices connected to the I2C bus are connected to the SCL of the bus, and their data lines SDA are connected to the bidirectional data line SDA of the bus. The bus uses software addressing to identify each device (such as microcontrollers, memories, LCD drivers, clock chips, and other I2C bus devices), completely eliminating the need for chip select lines for each device, thus making system wiring very simple. At present, I2C ...

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Application Information

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IPC IPC(8): G06F13/42
CPCG06F13/4291
Inventor 于克泳董强邵国刘嵘
Owner ZTE CORP
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