Semiconductor device having dual-STI and manufacturing method thereof

Abstract

A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate (1)and an isolation structure(6a,6b) implemented by a silicon oxide film (6)formed on a surface of the silicon substrate. A depth(d1) of the isolation structure(6a) in the memory cell area is smaller than a depth(d2) of the isolation structure(6b) in the peripheral circuit area, and an isolation height(h1) of the isolation structure (6a)in the memory cell area is substantially the same as an isolation height(h2) of the isolation structure(6b) in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.

Description

technical field [0001] The present invention relates to a semiconductor device and a manufacturing method thereof, in particular to a dual-STI (Shallow Trench Isolation) semiconductor device and a manufacturing method thereof. Background technique [0002] In order to achieve miniaturization and high speed of semiconductor elements, it is necessary to reduce the pitch of isolation elements. In the past, the LOCOS (local oxidation of silicon: local oxidation of silicon) method was generally used as a method for forming element isolation regions, but this method still cannot meet the demand for miniaturization. Therefore, as an alternative to this LOCOS method, ST1 has recently been used. [0003] In the conventional STI manufacturing method, first, a silicon oxide film, polysilicon, and silicon nitride film are stacked on a semiconductor substrate such as a silicon substrate. Next, a resist for opening an element isolation region is formed by photolithography, and this is u...

AI Technical Summary

Problems solved by technology

As a result, there is a problem of lowering the reliability of the semiconductor device

[0013] Here, in the technology disclosed in JP-A-5-121537, since the depth of the groove is uniquely determined according to the width of the groove, there is a problem that the design of the deep groove portion and the shallow groove portion is limited.

In addition, since the isolation height is not involved, the above problems cannot be solved

[0014] In addition, in the technology disclosed in Japanese Patent Laid-Open No. 2001-44273, there is no double STI manufacturing technology for forming deep grooves and shallow grooves with different depths, and the above-mentioned problems cannot be solved.

[0015] Furthermore, in Stephen N, Keeney'A 130nm Generation High DensityE tox TM Flash Memory Technology', page 11.[online]; In the disclosed technology, the element isolation height of the deep trench is higher than that of the shallow trench low, can not solve the above problems

In addition, there is no disclosure of any technique for solving the problem of excess silicon oxide film remaining on the stepped portion between the memory cell region and the peripheral circuit region.

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