Performance in flash memory devices

Abstract

In a method of fabricating a semiconductor device, a gate oxide layer (60) is provided on a silicon substrate (62). A first polysilicon layer (64) is provided on the gate oxide layer (60), a dielectric layer (66) is provided on the first polysilicon layer (64), and a second polysilicon layer (68) is provided on the dielectric layer (66). Upon appropriate masking, en etch step is undertaken, etching the second polysilicon layer (68), dielectric layer (66), first polysilicon layer (64) and gate oxide layer (60) to remove portions thereof to expose the silicon substrate (62) and to form a stacked gate structure (72) on the silicon substrate (62). A rapid thermal anneal is undertaken for a short period time, i.e., for example 10-20 seconds, to grow a thin oxide layer (80) on the stacked gate structure (72). Then, another oxide layer (82) is deposited over the oxide layer (80) which was formed by rapid thermal anneal.

Description

Technical field [0001] The present invention generally relates to semiconductor devices, and in detail, relates to performance improvement of flash memory devices. Background technique [0002] One type of programmable memory unit is commonly called a flash memory unit. Such a flash memory cell may include a source electrode and a drain electrode formed in a silicon substrate or formed in a well formed in the silicon substrate. The flash memory cell includes a stacked gate structure formed on the silicon substrate. The area of ​​the silicon substrate under the stacked gate structure is known as the channel area of ​​the flash memory cell. [0003] The stacked gate structure of the flash memory cell includes a pair of polysilicon structures separated by an oxide layer. One of the polysilicon structures functions as the floating gate of the flash memory cell, and the other polysilicon structure functions as the control gate. The oxide layer separating the floating gate and the sili...

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Problems solved by technology

This results in a considerable drop in core gain or drop in drive current in the device, which can clearly have an adverse effect on device performance

In addition, it was found that this prolonged oxidation step causes oxidized regions 32, 34 to grow into the sides of floating gate 14A near its bottom (on each side of gate stack 22, see FIGS. 3 and 4).

These undesired oxidized areas 32, 34 can cause significant problems with the speed of device removal

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