FPGA logic unit functional model and universal logic unit containing computing method

Abstract

The invention belongs to the field of electronic design automation technique, concretely a functional model of FPGA logic cells and a universal logic cell packing algorithm. The model firstly extracts functional components from the FPGA logic cells, then using the connection of the functional components and multi-channel switch selectors to describe the whole structure of logic cells, successively making different configurations on the logic cells to generate many available functional circuits formed only by connection of logic cells and the model can widely describe the structure of logic cells of the existing FPGAs and obtain all logic functions of logic cells by their corresponding available functional circuits. Based on the functional model of FPGA logic cells, the invention advances a universal logic cell packing algorithmí¬FDUPack whose kernel idea is to repeatedly make circuit diagram mode matching on each available functional circuit in the user circuit and which is a universal algorithm of processing various logic cell packing problems.

Description

technical field [0001] The invention belongs to the technical field of electronic design automation (Electronic Design Automation, EDA), and in particular relates to a functional model of an FPGA logic unit and a general logic unit packing algorithm. technical background [0002] Literature [1] points out that a logic block (Logic block) is a component that implements user circuit logic in a Field Programmable Gate Array (Filed Programmable Logic Array, FPGA). Oblock) is the three major components of FPGA, such as figure 1 shown. [0003] Logical blocks can be divided into flat logical blocks (also known as logical units, excluding internal interconnections) and hierarchical logical blocks (also known as cluster-structured logical blocks, which contain multiple logical units and internal interconnection resources). interconnect switch matrix). With the development of FPGA structure, hierarchical logic blocks have gradually replaced planar logic blocks and become the mains...

AI Technical Summary

Problems solved by technology

Logic cluster is the simplest structural model of hierarchical logic blocks. Its internal logic unit BLE and internal interconnection switch matrix adopt the most simplified method. Its shortcomings are: first, the logic unit BLE structure It is the simplest structure that can realize combinatorial and sequential logic. It has simple functions and does not contain any special functional elements, so it is not optimized for the actual application field of FPGA; second, the internal interconnection switch matrix is ​​fully connected, so it is very waste of layout area

The reason is that for different logical unit structures, there is no good general functional model of logical units

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