Method for reducing analog-digital converter capacitance mismatch error based on capacitance match

Abstract

The invention discloses a reducing analogue digital converter capacitance dismatch error method in the integrated circuit design technique domain, which is characterized by the following: four work capacitances of analogue-digital converter are defined; the two capacitances which two roofs connects to input amplifier positive carry-in terminal are C1and C2; the capacitances which two roofs connects to input amplifier negative carry-in terminal are C3 and C4; C1 and C3 are the first pair of difference displacement volume; C2 and C4 are the second pair of difference displacement volume; the two pairs of difference displacement volumes are the difference sampling capacitance or difference feedback capacitance of grade circuit; comparing four work capacitances forms two pairs of new difference work capacitances; one pair of difference work capacitance with the smaller capacitance value is used for grade circuit difference feedback capacitance. The invention doesn't improve the circuit power consumption and doesn't reduce the load speed.

Description

technical field [0001] The invention relates to a method for reducing the capacitance mismatch error of an analog-to-digital converter based on capacitance pairing, in particular to a method for reducing the capacitance mismatch error by selecting and pairing capacitors, thereby improving the accuracy of the analog-to-digital converter. Integrated circuit design technology field. Background technique [0002] In the pipelined and circular analog-to-digital converter (hereinafter referred to as ADC) based on switched capacitor technology, the switched capacitor stage circuit is a basic component unit, and its signal processing performance determines the performance of the entire ADC. A typical switched capacitor stage circuit generally works in two phases, that is, the sampling phase and the amplifying phase. figure 1 The working principle of a typical 1.5-bit level circuit is given, where, figure 1 (a) The circuit connection of the stage circuit in the sampling phase is gi...

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Problems solved by technology

[0017] Compared with the other two errors, the processing of capacitance mismatch error is more difficult, and the existing calibration methods also have their own shortcomings

For example, for the error self-calibration technology, its disadvantage is that it usually needs to add complex capacitance error measurement and calibration circuits, and, in order to resist the influence of changes in the working environment, periodic repeated measurement and calibration are required, which will affect the normal operation of the circuit. continuity, or further increase the complexity of the self-calibration circuit; as another example, for the capacitance error averaging technique, its disadvantage is that it requires 2 sampling and amplification operations for each conversion, so the conversion speed is slower than that of 2-phase operation Typical stage circuit

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