Multi-bus automobile communication control module based on TCN

[0009] The present invention will be further described below in conjunction with the drawings and embodiments:

[0010] Refer to figure 1 , The present invention includes a CPU processor 1, a memory electrically connected to the CPU processor 1, a reset circuit 3, an LED 4, a clock circuit 5, a temperature control circuit 6, an alarm circuit 7, a power supply circuit 8. The CPU processor 1 also It is connected to the FPGA 10, and the FPGA 10 is connected to the memory 9, the CAN bus interface 12, and the MVB bus interface 11. The MVB bus interface 11 is also directly connected to the CPU processor 1, and the CPU processor 1 is also connected to the general communication interface 13.

[0011] Refer to figure 2 In this embodiment, the CPU processor 1 is connected with a reset circuit 3, LED4, a clock circuit 5, a temperature control circuit 6, an alarm circuit 7, a power supply circuit 8, and the memory 2 connected to the CPU processor 1 is SDRAM or SRAM2-1 , The memory 9 connected to the CPU processor 1 is a combination of NOR FLASH 9-1 and NAND FLASH 9-2, and the general communication interface 13 connected to the CPU processor 1 has RS485/RS422 interface 13-1, USB interface 13-2, Serial port 13-3 and Ethernet interface 13-4. Both the CPU processor 1 and the memory 9 are connected to the FPGA 10, and the MVB bus interface 11 and the CAN bus interface 12 are connected to the FPGA 10.

[0012] CPU processor 1: Uses the current internationally popular Intel company’s Xscale core embedded network processor IXP425. Its main frequency can reach 533MHz. It is a cost-effective system-on-chip SOC chip. Its main interfaces are: PCI interface , UTOPIA interface, USB interface, high-speed serial port, universal serial port, SDRAM interface, JTAG debugging port, and multiple general I/O ports. It also integrates resources such as four-way timers, 32K instruction cache and data cache; its core voltage As low as 1.3V, the power consumption is only 2W during high-speed operation; with three configurable speeds of 266MHz, 400MHz, and 533MHz, it is especially suitable for network-based control systems.

[0013] LED4: Set four general status indicator lights, used to indicate the CPU processor running status, MVB network status, fault display, and user application running status indication. The status indicator lights are driven by the CPU's GPIO port buffer.

[0014] Clock circuit 5: The clock device RTC is used for setting the system clock and data recording during fault diagnosis. RTC uses a serial interface chip, which is connected to the CPUGPIO port through SPI or IIC, and the RTC battery uses a capacitor backup method.

[0015] Temperature control circuit 6: used to measure the air temperature inside the VCM, and access the CPUGPIO port through SPI or IIC protocol to monitor the internal overheating of the VCM and other faults.

[0016] Alarm circuit 7: Set up an alarm output relay, which is buffered and driven by the GPIO port of the CPU to indicate the fault status of the VCM externally. The module's working power supply and relay alarm output are led by the panel X7. This socket has the characteristics of large current and easy PCB installation. It is the first choice for the railway industry.

[0017] Power supply circuit 8: The power supply circuit provides 5V, 3.3V, 2.5V, 1.3V power for the entire VCM. It is composed of a DC/DC switching power supply module and a low-dropout linear regulator chip. The working power supply voltage range of the module is DC24V~137V, and the rated output power is 12W. The power input stage is equipped with an inrush current limiter and a backup capacitor. The power interruption tolerance time is greater than 10ms, and the power failure interruption indication signal is provided to the CPU subsystem.

[0018] FPGA10: Composed of FPGA and corresponding configuration circuit, used to realize the protocol control and management of MVB, CAN, NAND FLASH, etc. and the arbitration of various buses.

[0019] MVB bus interface 11: MVB bus interface is one of the cores of VCM, providing a connection channel for VCM with MVB bus. It includes MVB communication controller, 1M byte communication memory TM, CPU interface buffer and control logic, and MVB bus physical layer interface. Realize MVB bus management and realize the gateway interface of CAN and Ethernet. The external interface adopts 3 DIN41652 standard 9-pin D-type connectors. The pin definition complies with the TCN standard and is led out by the panel X1-X3, where X3 is for bus monitoring. Used with program download.

[0020] CAN bus interface 12: Controller area network bus CAN, which is composed of CAN protocol processor dedicated chip or FPGA and isolated level conversion circuit to realize CAN bus management and gateway interface with MVB and Ethernet. The CAN interface is led out by the VCM panel X4 DIN41652 standard 9-pin D-type connector.

[0021] Reset circuit 3: Mainly realize power monitoring, ensure the CPU power-on sequence and software monitoring functions, ensure the normal operation of the software, and "wake up" the CPU to enter the reset state in time when the software "runs away" or crashes.

[0022] Memory 9: The use of NAND FLASH memory is a technological innovation and breakthrough. In the past, only NOR FLASH memory was used. The memory of this embodiment is composed of NOR FLASH and NAND FLASH, where NOR FLASH is used for program memory and fault recording. Each NOR FLASH has a capacity of 16 MB and is composed of multiple chips. NAND FLASH is used for fault history recording, with a capacity of 16MB~1GB, which is the first application in the field of train control. Because the NAND FLASH operation timing is complicated, the timing is simulated by GPIO or FPGA.

[0023] Memory 2: SDRAM or SRAM: The capacity is from 64 to 256MB, and there is no need to change the design when using SDRAM with different capacities. Operate at a clock frequency of 133MHZ. IXP425 provides an SDRAM controller, which can connect up to 4 pieces of SDRAM. After the real-time operating system RTOS is initialized in the memory, it copies the BOOT image and the RTOS application image to SDRAM for execution.

[0024] Universal communication interface 13: There are Ethernet interface, serial bus interface, USB interface and RS485/RS422 interface, which can meet the needs of various popular input and output interfaces.

[0025] Ethernet interface 13-4: Lead out through RJ45 industrial Ethernet connector to realize the conversion of MVB device and CAN device to Ethernet to facilitate high-speed data transmission; debugging and fault data downloading interfaces, downloadable programs, and monitoring CPU operating status And download fault history data to PC or vehicle monitoring equipment.

[0026] Serial bus interface 13-3: The serial interface is composed of CPU and serial port level conversion circuit. It is mainly used as a PC-based VCM device debugging terminal interface for debugging functions such as downloading and monitoring of the underlying program. The maximum baud rate is 115.2 Kbps.

[0027]USB interface 13-2: It is composed of CPU and interface circuit, which realizes the connection of PC and removable storage devices such as U disk, USBdisk and VCM, so as to realize the functions of VCM program download, parameter setting, fault history data download and so on.

[0028] RS485/RS422 interface 13-1: Provides a RS485/RS422 interface with photoelectric isolation, which is mainly used to provide a communication interface based on the multi-point RS485/RS422 standard protocol to facilitate connection with third-party equipment. The maximum baud rate is 1Mbps. This interface is led out from the VCM panel via X5 and X6DB9 plugs.

[0029] The working principle of the present invention: the CPU processor 1 is the core part of the overall communication management of the vehicle communication control module. On the one hand, it manages the communication buses of the universal communication interface 13, MVB bus interface 11, and CAN bus interface 12 to realize the gateway function, namely Data exchange and resource sharing among various fieldbus devices are realized through the above-mentioned communication bus. On the other hand, the collected information of each field device is processed and then transmitted to other field devices when necessary, so as to realize the control, diagnosis, and display of the entire system, and store the relevant information in the memory 9. Through the above-mentioned field bus, especially USB and Ethernet, it is very convenient to download information and data to PC and other ground processing systems for analysis and processing. FPGA 10 participates in communication protocol processing and realizes bus arbitration among various chips within the module. In addition to various I/O modules, the above-mentioned fieldbus devices also include displays and other actuators.