Synchronised clock providing device and realizing method

Abstract

The invention relates to a synchronous clock provider, which comprises main and backup units. Wherein, each unit comprises E1 / T1 chain interface unit to supply the interface with external BITS / SSU, with SSM information extraction and insertion functions and outputting synchronous reference clock and SSM message; it also comprises digit latch ring and local crystal vibrator for detecting the signal quality of input reference clock, tracking and locking the selected reference clock resource, an generating output clock frequency; and it comprises a microprocessor for controlling and managing the main / backup unit; and it comprises a distributing module and a driving module for distributing and driving the output clock. The invention provides a synchronous method with complete function, synchronous chain expandable function, and high accuracy over than Stratum-4 / 4E and Stratum-3. The invention has low cost, simple structure and complete main / backup switch ability, to be used in TDM remote exchanger or access gateway. The invention can be used as electric module or sub board to combine the main control circuit, etc.

Description

technical field [0001] The invention relates to a synchronous clock supply device and a realization method suitable for remote switching units, access gateways and small-capacity end offices. technical background [0002] In the digital communication network, the signal transmitted and exchanged is the bit stream after encoding the information, so it has a specific transmission bit rate. If it is required that various digital devices on the communication network can exchange data accurately with each other, It is necessary for the clock signals of various digital devices (or network elements) in the network to process the bit stream with the same frequency and the same phase, which is the synchronization problem of the digital communication network. [0003] In China Invention Patent No. ZL 99127042.8, a synchronous clock supply device is disclosed. As shown in Figure 1, the synchronous clock supply device includes two main and standby modules working in a hot backup state, ...

AI Technical Summary

Problems solved by technology

[0005] 1) The division of the functions of each unit leads to complex interfaces. For example, the processing of the input clock should refer to the feedback from the phase-locked unit, and the processing results should be sent to the central processing unit for judgment, and then generate relevant information to the input clock processing unit according to the judgment results. Select a reference clock, and finally feed it to the phase-locked unit for tracking and locking

In this way, there are many types and quantities of signals on the interfaces between the units, which makes the structure and control of the device too complicated

This shortcoming makes this invention can only be provided independently, and its expansion and portability are poor, and it is difficult to integrate into other products;

[0006] 2) Judging from its functional configuration, the device uses a large number of components and the cost is relatively high

[0007] 3) Can only receive 2.048MHz or 8KHz reference clock signal, does not provide E1 or T1 synchronous link interface, cannot receive and extract SSM (Synchronization Status Message) message inserted in E1 / T1 bit stream, so it cannot provide SSM reception and sending capabilities, that is, the design can only be used as a synchronous time receiving device, and cannot provide status information of the clock synchronization chain to other devices;

[0008] 4) Although the output clock processing unit of the above-mentioned synchronous clock supply device adopts the delay line technology to reduce the phase jump, it cannot be completely eliminated, and there is still the problem of the phase jump of the output clock during the master-standby switchover

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