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Method for producing space wall, cleaning method after etching thereof and semiconductor element

A manufacturing method and technology of spacers, which are applied in semiconductor device, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problem that the width of the spacer is not easy to control, etc.

Active Publication Date: 2007-03-21
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Another object of the present invention is to provide a cleaning method after spacer etching, which can solve the problem that the width of the spacer is difficult to control
[0007] Another object of the present invention is to provide a semiconductor element with a spacer protection layer to protect the spacer from damage and loss

Method used

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  • Method for producing space wall, cleaning method after etching thereof and semiconductor element
  • Method for producing space wall, cleaning method after etching thereof and semiconductor element
  • Method for producing space wall, cleaning method after etching thereof and semiconductor element

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Embodiment Construction

[0037] 1A to 1D are cross-sectional views of the manufacturing process of a spacer according to an embodiment of the present invention.

[0038] First, please refer to FIG. 1A , a device structure 102 is formed on a substrate 100 . Wherein, the substrate 100 is, for example, a silicon substrate. The device structure 102 may be composed of, for example, a gate structure 102a and a source / drain region 102b, and the method and materials for forming the device structure 102 are well known to those skilled in the art, and will not be repeated here.

[0039] Then, referring to FIG. 1B , a spacer material layer 106 is formed on the substrate 100 to cover the entire substrate 100 and the device structure 102 . The material of the spacer material layer 106 is, for example, silicon nitride, and its formation method is, for example, chemical vapor deposition. In one embodiment, before the spacer material layer 106 is formed, a silicon oxide layer 104 may be formed on the substrate 100 ...

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Abstract

A clearance wall manufacturing method: provides the base formed the element structure, the element structure includes the gird structure and the fountain pole / the leaking pole; forms the clearance wall material layer on the base in order to cover the base and the element structure; processes etch craft, moves part of the clearance wall material layer to form clearance wall of the grid structure side-wall; processes the plasma processing step to form the clearance wall protective layer on the surface of the base, the clearance wall and the element.

Description

technical field [0001] The invention relates to a semiconductor element and technology, in particular to a manufacturing method of a spacer wall, a cleaning method after etching, and a semiconductor element. Background technique [0002] Conventionally, during the manufacturing process of metal oxide semiconductor transistors (MOS), a spacer is formed on the sidewall of the gate to help the isolation between the gate and the source / drain. Most importantly, the source / drain doping (doping) step is performed using the entire structure formed by the spacer and the gate. [0003] Generally speaking, a gate spacer process sequentially forms a gate oxide layer and a polysilicon layer on a semiconductor substrate. Then, the gate oxide layer and the polysilicon layer are defined to form a gate structure and so on. In this process, a silicon nitride layer is firstly formed to completely cover the entire gate structure, and then an etching step is performed to form silicon nitride s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/335H01L21/3105H01L29/772
Inventor 王传凯陈薏新刘家瑞陈瓀懿林明邑
Owner UNITED MICROELECTRONICS CORP