Semiconductor memory

Abstract

A semiconductor memory having a clock-synchronized burst mode read function and including a memory array constituted by a plurality of memory elements; a synchro-read control circuit that outputs, in synchronism with a clock, the upper order address of an address as a memory access address and also outputs, in synchronism with the clock, the lower order address as a burst address; a sense amplifier that outputs the output data of a memory element selected by the memory address; a decoder that decodes the burst address; an address latch that latches the burst address in synchronism with the clock; a page selector that holds the output data and selects the held output data in accordance with the burst address of the address latch; and an output latch that latches the output data in synchronism with the clock.

Description

technical field [0001] The present invention relates to a semiconductor storage device that stores data in correspondence with addresses, and more particularly to a semiconductor memory that has a function of reading data in a burst mode. Background technique [0002] Among semiconductor memories, flash memory is an electrically erasable memory with non-volatile characteristics such that the stored data is not lost when the power is cut off. Since it does not require a battery to keep data, it is mostly used in small portable devices in recent years. (especially mobile phone) storage device. [0003] Currently, the third generation of mobile phones is in service, applications such as Java (registered trademark) application execution and animation processing are diversified, and demands for larger internal memory, higher speed, and lower power consumption are increasing. [0004] In the flash memory described above, there is a synchronous burst read mode (hereinafter referre...

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Problems solved by technology

[0036] However, due to the limitation of setting time, the high-speed transmission path is limited, the operating frequency of the internal clock K cannot be increased, and the timing of output data varies with the clock frequency value, which cannot meet the requirements for high-speed access time.

[0037] In addition, there is no other way to achieve speed-up with the conventional method, or to improve the performance of MOS transistors, or to reduce the size of the chip, etc. to meet the requirements.

[0038] However, in order to improve the performance of MOS transistors, it is necessary to spend a lot of labor, time and money, and it is difficult to meet the requirements of high-speed operation.

[0039] In addition, reducing the size of the chip requires the miniaturization of the process, which leads to an increase in manufacturing costs due to equipment investment, resulting in a high unit price of the chip. Moreover, there is a certain limit to reducing the size using the existing process, so in order to increase the operating speed. Significantly reducing chip size is not realistic

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