Directly electric connected crystal covered encapsulation structure of semiconductor chip

Abstract

This invention relates to semiconductor chip direct electricity connection with film sealing structure, which comprises the following parts: at least one dielectric layer; at least one semiconductor chip with connection pad by main surface set on the dielectric layer; at least one circuit layer formed on the dielectric layer on one side of chip; conductor electrode formed on dielectric layer; electricity connection pad to semiconductor chip.

Description

technical field [0001] The invention relates to a direct electrical connection flip-chip packaging structure of a semiconductor chip, in particular to a direct electrical connection flip-chip packaging structure of an integrated semiconductor chip and a thinned semiconductor chip. Background technique [0002] With the vigorous development of the electronic industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of high integration and miniaturization of semiconductor packages, circuit boards that provide multiple active and passive components and line connections have gradually evolved from single-layer boards to multi-layer boards ( Multi-layer bord), in a limited space, uses the interlayer connection technology to expand the available wiring area on the circuit board to meet the needs of high-density integrated circuits (Integrated circuit). [0003] ...

AI Technical Summary

Problems solved by technology

[0007] However, the manufacturing process of the flip-chip ball grid array package, the process of electrically connecting the chip packaging substrate 12 and the semiconductor chip 10 to the chip packaging substrate 12 and packaging is a separate production mode, that is, the chip packaging substrate 12 is an independent manufacturing process. The packaging of the semiconductor chip 10 to the chip packaging substrate 12 is another independent process. The two independent processes will cause problems of low yield and long production cycle. After the electrical function is improved to a certain level, it cannot be effectively improved.

Although the flip-chip ball grid array (FCBGA) structure can be used in products with more pins and higher frequencies, the overall packaging cost is high, and there are still many technical limitations, especially in the electrical connection part, because Due to environmental protection requirements, electrical connection materials, such as lead (Pb) in solder materials, will be banned, and the use of other alternative materials will lead to unstable electrical, mechanical and physical properties.

[0008] Due to the fact that the existing Flip-Chip Ball Grid Array (FCBGA) packaging process is a separate process, there is a lack of low yield and long production cycle, which leads to increased production costs and cannot improve competitiveness, which has become an urgent issue in the industry.

Images