Safety detecting method for system integrated chip with built-in non-volatile memory

Abstract

The invention discloses a safe test method for an SOC (system on chip) embedded with nonvolatile memory (NVM), detecting data at embedded NVM specific addresses by a test mode detecting logic so as to implement test mode switching, where the embedded NVM specific addresses can not be accessed in user mode, and when the test is finished, it writes the appointed mode setting data at the embedded NVM specific addresses, and after detecting the data, a test mode logic circuit of the SOC intermediately switches the chip to the user mode to cut off test circuits of internal modules so as to make the chip enter into common user mode, thus implementing access inhibition to the internal modules. For reentering into the chip test mode, the invention also erases the mode setting data in the NVM by a special microprocessing instruction and simultaneously erases all data in the NVM so as to protect data.

Description

technical field [0001] The invention relates to an integrated circuit testing method, in particular to a system integrated chip safety testing method. Background technique [0002] Wafer-level testing of system integrated chip (SOC) products often involves the testing of internal logic function modules, analog IP modules and memory. Based on the protection of circuit design intellectual property rights and data security considerations, it is necessary to test The path is cut off, so that ordinary users can only use the functions in user mode, but cannot directly access the circuit modules inside the SOC and the data information in specific storage areas. Such tests are called security tests. [0003] Implementing chip security testing by changing the physical connection is a relatively common design technology at present. There are two main methods, one is fuse cutting, and the other is dicing groove cutting. [0004] The fuse cutting technology is to switch between the tes...

AI Technical Summary

Problems solved by technology

[0006] The above scheme of implementing chip security testing by changing the physical connection has the following problems: the physical change method is a destructive method, and the test mode cannot be re-entered after the change, and the application is not flexible; the user may realize the re-entry of the test mode through a physical repair method , and obtain circuit data information, the security is not high

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