Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method for forming a semiconductor structure are disclosed. A form of a method for forming a semiconductor structure includes: providing a base; patterning the base, to form a substrate and fins protruding out of the substrate, where each fin includes a bottom fin and a top fin located on the bottom fin, and in a direction perpendicular to an extension direction of each fin, a width of the top fin is less than a width of the bottom fin; and forming an isolation structure on the substrate exposed by a fin, where the isolation structure covers at least a sidewall of the bottom fin, and a top of the isolation structure is lower than a top of the fin. In the present disclosure, a bottom fin with a larger width is formed, to increase the volume of the bottom fin, and the area of a contact surface of the fin and the substrate, and to correspondingly enhance an effect of dissipating heat generated during working of a device to the substrate, thereby improving the heat dissipation performance of the device, and to correspondingly improving a self-heating effect of the device, so that the device performance is further improved.

Description

RELATED APPLICATIONS[0001]The present application claims priority to Chinese Patent Appln. No. 201811368089.1, filed Nov. 16, 2018, the entire disclosure of which is hereby incorporated by reference.BACKGROUNDTechnical Field[0002]Embodiments and implementations of the present disclosure relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof.Related Art[0003]In semiconductor manufacturing, with a development tendency of ultra-large-scale integrated circuits, a critical dimension (CD) of an integrated circuit is regularly being reduced. To adapt to the reduction of the CD, a corresponding channel length of a MOSFET is also regularly reduced. However, with the shortening of the channel length of a device, a corresponding distance between a source and a drain of the device is also shortened. Therefore, a control capability of a gate for a corresponding channel becomes worse, and it is increasingly difficult for a ...

AI Technical Summary

Benefits of technology

This patent describes a transition from planar MOSFET to three-dimensional FinFET transistors in a semiconductor process to improve device performance. Compared with planar MOSFETs, FinFETs have stronger control capability and better heat dissipation performance. The patent also provides improvements in the bottom fin volume and contact surface area for better heat dissipation and self-heating performance. Additionally, the patent describes a method for controlling the width of the bottom fin to further enhance the heat dissipation and self-heating performance of the device.

Problems solved by technology

Therefore, a control capability of a gate for a corresponding channel becomes worse, and it is increasingly difficult for a gate voltage to pinch off the channel, so that a subthreshold leakage phenomenon, that is, a so-called short-channel effect (SCE) occurs more easily.

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