Pll cycle slip compensation

Abstract

Phase-reset circuits provide first and second frequency-divided input signals to a phase / frequency detector (PFD) used in a phase-locked loop (PLL). The phase-reset circuits receive first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD generates control signals based on the phase difference between the frequency-divided input signals. Normally, the phase-reset circuits frequency divide the first and second input signals using divisors N and M, respectively. If other circuitry detects that the PFD has missed a clock cycle in the first or second clock-divided input signals, the corresponding phase-reset circuit alters its divider so that the next clock edge on the corresponding input signal clocks through to the PFD. This causes the PFD to quickly set its affected control signal to what it would have been had the clock cycle not been missed.

Description

[0001] represent a reference clock signal and an adjustable clock signal that is locked to the reference clock signal by operation of the PLL. When the detector's output signal(s) are generated as a function of the phase difference between the two input signals, the output signals accurately reflect the phase difference between the two input signals only when that difference is within a defined range. Generally, phase detectors used within PLL circuits cannot linearly detect when the phase difference between its two input signals is greater than .+-.2.rho. radians.BRIEF SUMMARY OF THE INVENTION[0002] The present invention is a system and method for reducing phase detection error in a phase / frequency detector (PFD) arising from cycle slip. The PFD compares arrival time differences between respective clock edges in two input signals and provides control outputs based on the phase difference between these clock edges. When the PFD misses a clock edge in either input signal, cycle slip ...

AI Technical Summary

Benefits of technology

[0002] The present invention is a system and method for reducing phase detection error in a phase / frequency detector (PFD) arising from cycle slip. The PFD compares arrival time differences between respective clock edges in two input signals and provides control outputs based on the phase difference between these clock edges. When the PFD misses a clock edge in either input signal, cycle slip occurs. Phase-reset circuits couple the two input signals to the PFD and operate as input frequency divider circuits, providing the PFD with a sub-harmonic of each input signal. Each phase-reset circuit normally operates as an up (or down) counter, providing one output clock cycle to the PFD for every N input signal clock cycles. When presented with an indication of cycle slip, however, the phase-reset circuit sets its divide-by counter to a value that causes the next input signal clock cycle to produce an output clock cycle. This action results in the cycle slip causing substantially less than the 2.rho. radians per missed cycle of phase error that otherwise manifests itself in the PFD control outputs.

Problems solved by technology

When the PFD misses a clock edge in either input signal, cycle slip occurs.

This action results in the cycle slip causing substantially less than the 2.rho. radians per missed cycle of phase error that otherwise manifests itself in the PFD control outputs.

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