Bus interface circuit and receiver circuit

Abstract

A bus interface circuit includes a precharge circuit including a switch element which is inserted between a bus line and a precharge power supply, receives a precharge control signal PE at its control terminal, and is turned on when the precharge control signal is active. The precharge circuit precharges the bus line to a predetermined precharge voltage from the precharge power supply via the switch element that is turned on. The precharge voltage is a predetermined voltage between a high-potential power supply voltage VDD and a low-potential power supply voltage VSS. When a signal received by an output circuit for output to the bus line has a first logic value, an output circuit sets the bus line, which has been precharged to the precharge voltage, from the precharge voltage to the predetermined VSS.

Description

[0001] The present invention relates to a bus interface, and more particularly to a bus interface comprising an output circuit that drives a bus line, a precharge circuit that pre-charges the bus line, and a receiver circuit that receives a signal output to the bus line.[0002] A conventional bus control system for use in a memory device will be described. FIG. 8 is a diagram schematically showing an example of a conventional system configuration of a memory device. Referring to FIG. 8, a plurality of memory cell sub-array blocks 200.sub.l-200.sub.m are connected to a common bus line 210 to which a receiver circuit 220 is connected. The receiver circuit 220 receives data read from the sub-array blocks 200.sub.l-200.sub.m and outputs the received data.[0003] The sub-array blocks 200.sub.l-200.sub.m each have the same configuration, with the configuration of the sub-array block 200.sub.l shown in the figure. The sub-array block 200.sub.l comprises a memory cell array 201 in which a plu...

AI Technical Summary

Benefits of technology

The present invention provides a bus system, a bus interface circuit, a receiver circuit, and a semiconductor device that can operate at high speed with restraints on power consumption. The invention includes a precharge circuit that preloads the bus line to a predetermined voltage, which is determined by a precharge control signal. The precharged bus line is then driven to a fixed voltage when a signal is output to the bus line, reducing the amplitude of the signal sent to the bus and reducing the time required for the output circuit and the receiver circuit to access the bus. The invention also includes a logic amplitude adjustment feature that allows for different signal levels to be output to the bus based on the power supply voltage levels. The invention provides faster and more efficient operation with lower power consumption.

Problems solved by technology

This delay time results in an increase in access time and becomes one of the limiting factors of the high-speed operation of the memory system.

On the other hand, an increase in current drive capability of the output buffer circuit in an attempt to speed up a transition time of a signal at the far-end of the bus line would lead to an increase in power consumption.

Images