Method and apparatus for reducing on-chip memory in vertical video processing

Abstract

A digital image processor includes an input buffer for storing raster-scanned data. A slice-buffer memory is coupled to the input buffer to store a portion of a vertical slice of said raster-scanned data. The vertical slice is processed by a vertical slice processor having an input coupled to the slice-buffer memory. The vertical slice processor reassembles the vertical slices into processed raster-scanned data in an output buffer that is coupled to the output of the vertical slice processor. The digital image processor preferably utilizes multiple sequential processing stages and processes the raster-scanned data along the horizontal axis of the vertical slices.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims the benefits of co-pending U.S. Patent Provisional Application No. 60 / 093,815 filed on Jul. 23, 1998, and is related to U.S. patent application Ser. No. 09 / 167,527 filed on Oct. 6, 1998, both of which are incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates generally to video processing and, more particularly, to techniques for vertical processing of horizontally scanned video images. [0004] 2. Description of the Related Art [0005]FIG. 1 shows an illustration of a rectangular picture area 10 with a horizontal full row scanning sequence. The rectangular picture area 10 is divided into a number of rows of data 12 which are scanned from left to right, with rows being traversed from the top of the image to the bottom. Video data is generally produced in this type of horizontal raster-scanned format. Video data is also provided in this fashi...

AI Technical Summary

Benefits of technology

[0018] An advantage of the present invention is that the on-chip-memory requirements for high quality vertical processing are significantly reduced. By dividing the rectangular video field or frame into smaller portions, the memory requirements of the system can be reduced by an order of magnitude. Therefore, the image processing chip is not limited by the constraints of having only a small number of on-chip line memories. In addition, by not having to use the line memories, costs are dramatically reduced.

Problems solved by technology

However, when video data must be processed in the vertical direction, particularly when multiple vertically adjacent pixel locations are simultaneously needed for processing, the raster-scanned format no longer provides the data needed in the correct or appropriate order. FIG. 3 is a diagram of a horizontal raster-scanned video image 20 divided into a number of scan lines 22 and pixels 24.

In the past, this has either not been done at all due to implementation cost reasons, or has been done by using multiple on-chip line memories to store a number of horizontal lines of pixel data.

If nothing is done, the result is nonexistent or poor quality processing due to lack of vertical pixel data being available.

The main problem with using on-chip line memories for vertical processing of horizontal raster-scanned video is that they are extremely large, thus requiring a significant increase in die area (and therefore chip cost).

External memories have not been often utilized due to the fact that accessing vertically adjacent data results in the crossing of DRAM row (or page) boundaries, with the attendant severe reduction in available memory bandwidth.

The implementation cost issue is compounded by the fact that high quality processing typically requires more data, i.e., better vertical processing requires a larger number of simultaneously available vertically aligned pixels.

On-chip memory requirements of this order significantly reduce the available implementation options (e.g., prototyping with field programmable gate arrays (FPGA) or most gate-arrays is not viable) and increase the chip die area and cost.

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