Methods of treating non-sputtered regions of PVD target constructions to form particle traps

a technology of non-sputtered regions and traps, applied in vacuum evaporation coatings, electrolysis components, coatings, etc., can solve the problems of large particle formation, large particle formation, and affecting the desired properties of the film

Inactive Publication Date: 2005-04-21
HONEYWELL INT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Problems can occur in deposition processes if particles are formed, in that the particles can fall into a deposited film and disrupt desired properties of the film.
Although some of the textured surfaces have been found to reduce particle formation, the particle formation is frequently not reduced to a desired level.
In some instances, the texturing on a sidewall surface of a target can ultimately lead to formation of very large particles.
The films can fall onto a substrate during a PVD process to cause a defect in a lay

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  • Methods of treating non-sputtered regions of PVD target constructions to form particle traps
  • Methods of treating non-sputtered regions of PVD target constructions to form particle traps
  • Methods of treating non-sputtered regions of PVD target constructions to form particle traps

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Embodiment Construction

[0030] This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).

[0031] The invention encompasses new textures which can be formed on one or more surfaces of a PVD target or target / backing plate assembly, and utilized for trapping sputtered materials which redeposit on the target or assembly. In a particular aspect, curved projections (such as, for example, a bent scroll pattern) are formed on non-sputtered surfaces of a target or target / backing plate assembly to form particle trapping areas. The non-sputtered surfaces can include sidewall surfaces, flange surfaces and / or non-sputtered surfaces along a sputtering face. The projections can be exposed to particles to roughen surfaces of the projections. The projections can be considered to form a macro-scale roughness of a trapping area, and the roughened surfaces of the projections can be considered t...

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Abstract

The invention includes PVD targets having non-sputtered regions (such as, for example, sidewalls), and particle-trapping features formed along the non-sputtered regions. In particular aspects, the particle-trapping features can comprise a pattern of bent projections forming receptacles, and can comprise microstructures on the bent projections. The targets can be part of target/backing plate constructions, or can be monolithic. The invention also includes methods of forming particle-trapping features along sidewalls of a sputtering target or along sidewalls of a target/backing plate construction. The features can be formed by initially forming a pattern of projections along a sidewall. The projections can be bent and subsequently exposed to particles to form microstructures on the bent projections.

Description

RELATED PATENT DATA [0001] This patent claims priority to U.S. Provisional Patent Application 60 / 396,543, which was filed Jul. 16, 2002.TECHNICAL FIELD [0002] The invention pertains to methods of forming particle traps along non-sputtered regions of a physical vapor deposition (PVD) target construction, and pertains to PVD target constructions having projections along at least one non-sputtered region. BACKGROUND OF THE INVENTION [0003] Deposition methods are utilized for forming films of material across substrate surfaces. Deposition methods can be utilized in, for example, semiconductor fabrication processes to form layers ultimately utilized in fabrication of integrated circuitry structures and devices. An exemplary deposition method is physical vapor deposition (PVD), which includes sputtering processes. [0004] A physical vapor deposition operation is described with reference to a sputtering apparatus 110 in FIG. 1. Apparatus 110 is an example of an ion metal plasma (IMP) appara...

Claims

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Application Information

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IPC IPC(8): C23C14/34
CPCC23C14/3407H01J37/3491H01J37/3435H01J37/3414C23C14/081C23C14/0635
Inventor KIM, JAEYEON
Owner HONEYWELL INT INC
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