NROM flash memory devices on ultrathin silicon

Abstract

An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.

Description

TECHNICAL FIELD OF THE INVENTION [0001] The present invention relates generally to memory devices and in particular the present invention relates to nitride read only memory flash memory devices. BACKGROUND OF THE INVENTION [0002] The increased speed and capability of computers and other electronic devices requires better performance from the integrated circuits that make up a device. One way to make the integrated circuits faster is to reduce the size of the transistors that make up the device. However, as transistors are made smaller and faster, delays through the connections between the transistors becomes greater in relation to the speed of the transistor. [0003] An alternative technique to speed up integrated circuits is to use alternative semiconductors. For example, silicon-on-insulator (SOI) technology provides a 25-35% performance increase over equivalent CMOS technologies. SOI refers to placing a thin layer of silicon on top of an insulator such as silicon oxide or glass. ...

AI Technical Summary

Benefits of technology

[0008] The above-mentioned problems with eliminating floating body effects and other problems are addressed by the present invention and will be understood by reading and studying the following specification.

Problems solved by technology

However, as transistors are made smaller and faster, delays through the connections between the transistors becomes greater in relation to the speed of the transistor.

SOI technology, however, imposes significant technical challenges.

It is very difficult to make perfect crystalline silicon-on-oxide or silicon with other insulators since the insulator layer's crystalline properties are so different from the pure silicon.

If perfect crystalline silicon is not obtained, defects will find their way onto the SOI film.

This degrades the transistor performance.

Additionally, floating body effects in partially depleted CMOS devices using SOI technology are undesirable in many logic and memory applications.

In dynamic logic and DRAM memories, the floating bodies cause excess charge leakage and short retention times that can cause data loss.

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