Wafer, semiconductor chip, and semiconductor device manufacturing method

Abstract

Scribe lines demarcating semiconductor chips comprise, in both the vertical direction and the horizontal direction, first-type scribe lines of the minimum width enabling cutting by dicing or other means, and second-type scribe lines enabling placement of TEGs, alignment marks or other accessories, and a placement pattern is set so that a unit cell which can be exposed in a single shot comprises one second-type scribe line. By this means, the area occupied by scribe lines can be reduced. Further, by decreasing the number of placement of semiconductor chips constituting a unit cell, and by cutting substantially along the center line of second-type scribe lines, the shapes of scribe lines on the periphery of semiconductor chips can be changed, so that the position in the unit cell can be determined.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates to a semiconductor chip and semiconductor device manufacturing method which facilitates defect inspection, and a wafer for obtaining such a semiconductor chip. [0003] 2. Description of the Related Art [0004] In order to achieve lower costs for semiconductor chips, it is important that the number of semiconductor chips obtained from a single wafer be increased. As shown in FIG. 10, wafers generally comprise a plurality of semiconductor chips 3 arranged in a matrix, and scribe lines 9 of a prescribed width provided between the individual semiconductor chips 3. A dicing system or similar is used to cut the wafer 1 along the scribe lines 9, to divide the wafer into individual semiconductor chips 3. [0005] A TEG (Test Element Group) comprising check transistors is formed on the wafer 1; this TEG is used to judge the quality of semiconductor chips 3 at the wafer stage. However, if a TEG is formed wi...

AI Technical Summary

Benefits of technology

[0010] For example, the scribe lines provided on a wafer for division into a plurality of semiconductor chips arranged in a matrix comprise, in both placement directions (the vertical direction and the horizontal direction), first-type scribe lines, of the minimum width enabling cutting using dicing, laser machining, anisotropic etching, or other means, and scribe lines of a plurality of other widths, comprising second-type scribe lines and third-type scribe lines, with line widths larger than those of first-type scribe lines so as to enable placement of TEGs comprising check transistors, alignment marks, and similar. A scribe line placement pattern is set preferably such that, within a region which can be exposed in a single shot (a unit cell), one second-type scribe line or third-type scribe line in both the vertical direction and in the horizontal direction is comprised. By this means, compared with a configuration employing only thick scribe lines, the area occupied by scribe lines can be reduced, so that the number of semiconductor chips which can be obtained from a single wafer can be increased, and consequently semiconductor chip cost reduction can be achieved.

[0011] In another aspect of the in...

Problems solved by technology

It has now been discovered that by using the above method, compared with a method of making scribe lines wider in both the vertical direction and the horizontal direction, the number of semiconductor chips obtained from a single wafer can be increased; but when the shape of semiconductor chips is nearly square, the area occupied by scribe lines in one direction (the above-described first dividing area) is increased, and the number of semiconductor chips obtained cannot be increased so much.

In structures of the above related art, the widths of scribe lines adjacent to the upper, lower, left and right edges of ea...

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