Wiring structure for integrated circuit with reduced intralevel capacitance

Abstract

A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.

Description

BACKGROUND OF INVENTION [0001] This invention relates to the manufacture of large-scale integrated semiconductor devices, and more particularly to a structure and method for reducing the capacitance in a dielectric layer between metal features in such devices. [0002] Ultra-large scale integrated (ULSI) semiconductor devices typically include several layers having metal wiring features (metallization layers) disposed on the top surface of the device, separated from each other in the vertical direction by insulating layers of dielectric material (interlevel dielectric layers). This arrangement of multiple wiring layers and insulating layers is required in order to provide interconnects between devices. The structure of metallization and interlevel dielectric layers is often realized using a damascene process, wherein a pattern is etched into a dielectric layer, the patterned layer is covered with metal and then polished (leaving metal embedded in the etched features), and the metalliz...

AI Technical Summary

Benefits of technology

[0005] The present invention provides a process for forming air gaps adjacent to the conductors in a metallization layer, with the air gaps being at sub-lithographic dimensions. These features result in a series capacitance between the conductors which is lower than the capacitance of the bulk dielectric, thereby reducing the intralevel capacitance. The present invention also provides a stack of low-k material, an air gap, and additional low-k material, forming a sandwich structure which minimizes fringing capacitance.

[0007] According to another aspect of the invention, a wiring structure is provided which includes a plurality of conductors with dielectric layers above and below. A plurality of conductors is disposed on a first dielectric layer; the conductors are separated laterally from each other by portions of a second dielectric layer and by air gaps. Each of the conductors has air gaps adjacent thereto separating the conductor from the second dielectric layer. A third dielectric layer overlies the conductors. Each of the conductors has a cross-section wider at a top thereof than at a bottom thereof, in accordance with each of the air gaps having a cross-section wider at a bottom thereof than at a top thereof. The first and third dielectric layers may each have a dielectric constant less than that of the second dielectric layer. Accordingly, a cross-section of each of the conductors has a bottom in contact with the first dielectric layer, a top in contact with the third dielectric layer, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.

Problems solved by technology

As the dimensions of ULSI devices continue to shrink, the performance of the devices is increasingly limited by the capacitance of the interlevel dielectric.

For example, the capacitance of the interlevel dielectric influences the device speed (due to the RC delay in the structure of wiring and insulators), the AC power consumption of the device, and crosstalk.

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