Address generators integrated with parallel FFT for mapping arrays in bit reversed order

Abstract

Reducing the amount of required memory and instruction cycles when implementing Fast Fourier Transforms (FFTs) on a computer system is described. The invention optimizes FFT software using in-place bit reversal (IPBR) implemented on a processor capable of bit reversed incrementation. Enables the design of address generators that combine IPBR and one FFT stage in parallel. Increases efficiency by removing instructions to store output from a stand-alone IPBR mapping and then fetch the same data as input for the FFT stage.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation-in-part of U.S. patent application Ser. No. 10 / 097,407, entitled “ADDRESS GENERATORS FOR MAPPING ARRAYS IN BIT REVERSED ORDER,” filed on Mar. 15, 2002.FIELD OF THE INVENTION [0002] The present invention is a method and apparatus to reduce the amount of required memory and instruction cycles when implementing Fast Fourier Transforms (FFTs) on a computer system. More particularly, the preferred embodiment of the present invention optimizes FFT software using in-place bit reversal (IPBR) implemented on a processor capable of bit reversed incrementation. BACKGROUND OF THE INVENTION [0003] Algorithms that perform discrete transforms such as Fast Fourier Transforms (FFTs) are well known. The Fourier transform is a mathematical operator for converting a signal from a time-domain representation to a frequency-domain representation. The inverse Fourier transform is an operator for converting a signal from a fre...

AI Technical Summary

Benefits of technology

[0023] The present invention improves the in-place bit reversal (IPBR) process on computer processors and systems by defining an address generator for generating address pairs used for processing an input array using IPBR in parallel with processing a stage of a Fast Fourier Transform (FFT). The method optimizes FFT software using IPBR that can be implemented on a processor.

[0024] The present invention creates an address pair generator that is used to combine IPBR and one FFT stage. Computing the IPBR and the first FFT stage in parallel increase processing efficiency by removing instructions to store output from a stand-alone IPBR mapping and then fetch the same data as input for the FFT stage.

Problems solved by technology

An FFT using OOPBR may have a hidden cycle penalty beyond the bit reversal itself, when the output is eventually copied back to the location of the input array.

Computational processes that use more of the available scratch memory than necessary can lead to future problems when converting to an operating system that permits multiple computational processes to interrupt each other.

In the event that the cycles required for IPBR can be made more competitive relative to OOPBR, for many applications the additional data memory requirement of OOPBR cannot be justified.

The conventional IPBR method is inefficient because it relies on an address pair generator that yields extraneous address pairs.

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