Comprehensive erase verification for non-volatile memory

Abstract

Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and / or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates generally to technology for programming non-volatile memory devices. [0003] 2. Description of the Related Art [0004] Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. [0005] One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series, sandwiched between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a top view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string dep...

AI Technical Summary

Benefits of technology

[0022] In accordance with one embodiment, groups of storage elements are read for an erased state only when they pass an erase verification process. Those cells that fail an erase verification process do not undergo further testing such as a read for erased state process. Accordingly, time costs incurred by implementing the extra read for erased state process are minimized.

Problems solved by technology

During manufacturing, it is possible that some flash memory devices or portions thereof become defective.

Individual transistors, strings, or blocks of storage elements may be defective and unusable.

Additionally, defects in the device may arise after the manufacturing process or during user operation.

If left undetected, however, defects can cause erroneous erase verification and in some cases, irretrievable user data.

Groups of cells having defective storage elements or select gates will not program or erase properly, indicating a problem with one or more of the devices in the string.

During manufacturing, defects in flash memory may be discovered during a number of routine testing operations that are performed as part of the manufacturing process.

During user operation, defects can be detected by cells, strings, or blocks that fail to erase or program properly.

Similarly, if a cell fails to program to a desired state after a number of attempts, it can be determined to be defective.

Although these techniques can discover some defects in a memory device and verify erasure to an extent, they may not fully verify that cells are erased and detect all defects in the device.

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