Semiconductor device having optimized shallow junction geometries and method for fabrication thereof

Abstract

The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134). Other embodiments of the present invention include a transistor device (200) and method of manufacturing an integrated circuit (300).

Description

TECHNICAL FIELD OF THE INVENTION [0001] The present invention is directed in general to the manufacture of semiconductor devices, and, more specifically, to a method of fabricating transistor devices having optimized shallow junction geometries. BACKGROUND OF THE INVENTION [0002] The continuing push to produce faster semiconductor devices with lower power consumption has resulted in the miniaturization of semiconductor devices. In particular, smaller gate oxide thickness and channel width are conducive to the low voltage and faster operation of transistor devices, such as complementary metal oxide (CMOS) transistors. With shrinking process geometries, comes a number of new design problems, however. [0003] For instance, as gate dimensions are reduced, it has become necessary to adjust and better control the dimensions of the channel and doped regions of the substrate that are associated with the gate. This is necessary to prevent a number of short channel effects, such as hot carrier...

AI Technical Summary

Benefits of technology

"The present invention provides a method of fabricating a semiconductor device by growing an oxide layer on a gate structure and substrate and implanting a dopant into the substrate and oxide layer. The method also includes forming etch-resistant off-set spacers adjacent sidewalls of the gate structure and on the protective oxide layer. The invention also provides a metal oxide semiconductor (MOS) transistor device and a method of manufacturing an integrated circuit by interconnecting the MOS transistor devices with interconnects to form an operative integrated circuit. The technical effects of the invention include improving the stability and reliability of semiconductor devices and reducing the size of integrated circuits."

Problems solved by technology

With shrinking process geometries, comes a number of new design problems, however.

Sub-0.1 micron transistor devices are also highly susceptible to leakage currents, or punch-through, when the transistor is off.

The formation of abrupt shallow junctions can be problematic in certain instances, however.

Small dopants, such as boron, are subject to undesirable enhanced diffusion into implantation-caused damage to the lattice structures of silicon substrates during thermal annealing.

This phenomenon, known as transient enhanced diffusion (TED), is undesirable because it decreases the abruptness of the change in dopant concentrations from the shallow junction to a p-well or n-well that the shallow junction is formed in.

TED can also cause dopants, such as boron, to diffuse into the channel region, thereby causing an unfavorable change in the dopant concentration in the channel resulting in punch-through, an increase in electron trapping, a decrease in low-field hole mobility, and a degraded on-current drive.

However, if the pocket regions on the source and drain sides of the transistor's channel region are too close to each other, then the pocket regions will overlap.

Overlap, in turn, causes excessively high resistance in the channel region, thereby undesirably reducing the on-current of the device.

This approach is not entirely successful, however, because the extent of diffusion of p-type and n-type dopants during thermal annealing are substantially different than each other.

Consequently, the fabrication steps used to mitigate the short channel effects in PMOS transistors are not necessarily beneficial to mitigate the short channel effects in NMOS transistors.

Indeed, if the junctions in an NMOS transistor are too far apart, this can detrimentally decrease the source to drain saturation current of the NMOS transistor, thereby reducing the operating speed of the device.

Heretofore, however, the fabrication processes for PMOS and NMOS transistors in CMOS devices have resulted in the formation of shallow junctions having substantially the same geometries.

As such, the geometries of one or both of the NMOS and PMOS shallow junctions have not been simultaneously optimized in both transistor types.

Because current CMOS devices are constructed with compromised NMOS and PMOS shallow junction geometries, the performance of these devices is also compromised.

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