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High coupling memory cell

a memory cell and high coupling technology, applied in the field of memory devices, can solve the problems of reducing the capacitance of the effective capacitor, the surface area of the floating gate of the cell also decreases, and the component dimensions

Inactive Publication Date: 2006-09-21
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach improves the programming and access performance of the memory cell by increasing capacitive coupling, addressing the challenge of reduced cell performance due to smaller dimensions.

Problems solved by technology

One problem, however, with decreasing cell component dimensions is that the surface area of the cell's floating gate also decreases.
This leads to a decrease in the capacitance of the effective capacitor formed between the floating gate layer and the control gate layer.
The decrease in effective capacitance results in a reduction of the capacitive coupling ratio.
The poorly coupled voltage to floating gate limits the programming and accessing speed characteristics of the memory device.

Method used

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Embodiment Construction

[0016] In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof. The term wafer or substrate used in the following description includes any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-...

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Abstract

A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.

Description

RELATED APPLICATION [0001] This Application is a Continuation of U.S. application Ser. No. 10 / 899,913, titled “HIGH COUPLING MEMORY CELL,” filed Jul. 27, 2004, (Pending) which is commonly assigned and incorporated herein by reference.TECHNICAL FIELD OF THE INVENTION [0002] The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices. BACKGROUND OF THE INVENTION [0003] Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. [0004] Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for h...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/336
CPCH01L27/115H01L27/11521H01L29/42324H01L29/7881H10B69/00H10B41/30
Inventor SANDHU, SUKESHSANDHU, GURTEJ S.
Owner MICRON TECH INC