System and method for connecting a logic circuit simulation to a network

a logic circuit and network connection technology, applied in data switching networks, cad circuit design, multiplex communication, etc., to achieve the effect of preventing network connection loss and small buffer memory

Inactive Publication Date: 2007-03-22
IONIPAS TRANSFER +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0008] In one embodiment, the present invention allows the interface software of a host computer to individually examine a data packet of a conventional off-the-shelf interface card to identify the beginning and the end of the packet. When the beginning and the end of a data packet can be identified, the interface software of the host computer ignores data packets not addressed to the simulated circuit. Consequently, compared to the prior art, a much smaller amount of buffer memory is required. This arrangement loses data packets only in the occasional event of a buffer overflow, thus effectively preventing network connection loss.

Problems solved by technology

Under this arrangement, the interface software in the host computer need not send to the circuit simulation, for example, the preamble required to synchronize the clocks of the network and the circuit simulation, because the circuit simulation is usually not capable of providing an analog interface required to respond to the preamble.

Method used

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  • System and method for connecting a logic circuit simulation to a network
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second embodiment

[0029]FIG. 6 is a block diagram 600 showing the functions performed by Molasses program 40, in accordance with the present invention. As in Molasses program 50 of FIG. 3, Molasses program 40 of FIG. 6 interfaces with network interface 74, which provides host computer 30's access to computer network 24, and interface 72, which couples host computer 30 to bidirectional interface 22 to circuit emulator 12. Interface 72 can be implemented by a conventional parallel port operating under, for example, the EPP standard. Once the parameters of Mainscreen 80 (FIG. 4) are set, Mainscreen 80 calls “W32N_MolassesStart” routine 52, which creates four threads 120, 122, 124 and 126. Thread 120 executes “W32_PacketRead” routine 58, which receives data packets from Ethernet NIC 74 and stores the received data packet into shared buffer 128 in the main memory of the host computer 30. Thread 122 executes “Port32_PacketSend” routine 64, which polls shared buffer 128 for the received data packets, repack...

third embodiment

[0034]FIG. 7 is a block diagram 700 showing the functions performed by Molasses program 750, in accordance with the present invention that can be implemented in the configuration of FIG. 9 Molasses program 750 can include a graphical user interface similar to that illustrated in FIG. 4 by Mainscreen 80. As in Molasses program 50, Molasses program 750 interfaces with network interface card (NIC) 74, which provides host computer 930's access to computer network 24, and simulation interface 772, which provides a program interface in host computer 930 to a circuit simulation running on host computer 930 concurrently with Molasses program 50. In this embodiment, simulation interface 772 can be a conventional programming language interface (PLI), an interprocess communication mechanism (e.g., a socket), a client-server type interface, or any other suitable software interface. For example, hardware description languages, such as Verilog or VHDL, provide support for programming interfaces. ...

fourth embodiment

[0036]FIG. 8 is a block diagram 800 showing the functions performed by Molasses program 840, in accordance with the present invention that can also be implemented in the configuration of FIG. 9. As in Molasses program 750 of FIG. 7, Molasses program 840 of FIG. 8 interfaces with network interface 74, which provides host computer 930's access to computer network 24, and simulation PLI 772, which couples host computer 930 to the running circuit simulation. Once the parameters of Mainscreen 80 (FIG. 4) are set, Mainscreen 80 calls “W32N_MolassesStart” routine 852, which creates four threads 820, 822, 824 and 826. Thread 820 executes “W32_PacketRead” routine 58, which receives data packets from Ethernet NIC 74 and stores the received data packet into shared buffer 128 in the main memory of the host computer 930. Thread 822 executes “SIM_PacketSend” routine 864, which polls shared buffer 128 for the received data packets, repackages these data packets and sends them to the running circui...

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Abstract

A system and method for connecting a running logic circuit simulation to a network running at a higher speed that includes a computer for receiving data packets from the network and storing the received data packets in a first buffer. The computer next transmits the received data packets to an electronic circuit in the logic circuit simulation at a slower speed. The computer also receives data packets from the electronic device under simulation, and stores the data packets received from the electronic device under simulation in a second buffer. The computer then transmits the data packets received from the electronic device under simulation to the network at a higher speed.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATION [0001] The present application is a continuation-in-part application of copending U.S. patent application, entitled “METHOD FOR CONNECTING A HARDWARE EMULATOR TO A NETWORK,” Ser. No. 09 / 751,573, filed on Dec. 28, 2000.BACKGROUND OF THE INVENTION [0002] Prior to reducing an integrated circuit design to a form suitable for fabrication, the integrated circuit design is often simulated in software on a computer, and emulated in hardware to allow the design to be optimized and debugged. Typically, using a hardware description language (e.g., VHDL), the circuit designer prepares a hardware description of the integrated circuit, which is then compiled into a software model to be simulated on a computer (e.g., an engineering workstation). Often, the hardware description can also be compiled into a hardware model that can be emulated in a hardware emulator. A hardware emulator suitable for such use typically includes field programmable gate array...

Claims

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Application Information

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IPC IPC(8): H04L12/56H04L12/26
CPCG06F17/5022H04L43/50H04L69/28H04L67/36H04L67/08G06F30/33H04L67/75
InventorZIEDMAN, ROBERT M.
OwnerIONIPAS TRANSFER