Structure and fabrication of self-aligned high-performance organic fets

Abstract

A low channel length organic field-effect transistor can be produced in high volume and at low cost. The transistor structure includes successively deposited patterned layers of a first conductor layer acting as a source terminal, a first dielectric layer, a second conductor layer acting as a drain terminal, a semiconductor layer, a second dielectric layer, and a third conductor layer acting as the gate terminal. In this structure, the transistor is formed on the edge of the first dielectric between the first conductor layer and the second conductor layer. The second conductor layer is deposited on the raised surfaces formed by the dielectric such that conductive ink does not flow into the trough between the dielectric raised surfaces. This is accomplished by coating a flat or rotary print plate with the conductive ink, and applying the appropriate pressure to deposit the materials only on the raised surfaces of the dielectric. The second metal is automatically aligned to the layer beneath it. Due to this self-alignment and the short channel formed by the thickness of the dielectric material, a high-performance FET is produced without the requirement of high-resolution lithography equipment.

Description

1. FIELD OF INVENTION [0001] The present invention relates to organic transistors and, more particularly, to a structure and method of fabricating high performing organic FETs utilizing an efficient high volume self-aligned patterning technique to produce low channel length organic FET devices. 2. DESCRIPTION OF RELATED ART [0002] Organic field-effect transistors (oFETs) have been proposed for a number of applications including displays, electronic barcodes and sensors. Low cost processes, large-area circuits and the chemically active nature of organic materials are the chief driving forces to make OFETs important in various applications. Many of these objectives depend on a method of fabrication utilizing printing techniques such as flexography, gravure, silk screen and inkjet printing. [0003] Organic MOS transistors are similar to silicon metal-oxide-semiconductor transistors in operation. The major difference in construction is that the organic MOS transistor utilizes a thin laye...

AI Technical Summary

Benefits of technology

[0014] According to the present invention, a structure and method of fabrication is disclosed that can produce low channel length devices in high volume and at low cost. The structure includes successively deposited patterned layers of a first conductor layer acting as a source terminal, a first dielectric layer, a second conductor layer acting as a drain terminal, a semiconductor layer, a second dielectric layer, and a third conductor layer acting as the gate terminal. In this structure, the transistor is formed on the edge of the first dielectric between the first conductor layer and the second conductor layer.

[0015] The second conductor layer is deposited on the raised surfaces formed by the dielectric such that the ink does not flow into the trough between the dielectric raised surfaces. In an embodiment of the invention, this is accomplished by coating a flat or rotary print plate with a conductive ink, and applying the appropriate pressure to deposit the materials only on the raised surfaces of the dielectric. In this manner, the second metal is automatically aligned to the layer beneath it. Due to this self-alignment and the short channel formed by the thickness of the dielectric material, a high-performance FET is produced without the requirement of high-resolution lithography equipment.

Problems solved by technology

However, the actual mechanics giving rise to charge carriers in organic semiconductors are substantially different from inorganic semiconductors.

Though organic transistors have much lower performance than inorganic transistors, the materials and processing techniques to produce organic transistors cost significantly less those used to produce inorganic transistors.

Therefore, organic transistor technology has application where low cost is desired and low performance is acceptable.

Low cost printing techniques are generally limited to a minimum range of 25μ.

Printing at resolutions finer than this is generally not possible.

The advantages of the short channel length that can potentially be obtained through vertical transistors is consequently lost.

However, several issues make this fabrication method impractical.

A serious problem with this method is that the metal 408 layer smears when pressing the impression die through the layers, thereby shorting second conductor 408 and first conductor 404.

Another problem with this method is that the die impression forms a point at the bottom of the device, which is very difficult to deposit layers of controlled thickness in this region.

One further problem with this method is that pressure controls the impression die depth of penetration.

If the impression die pressure is too heavy, the impression die will penetrate substrate 402, adversely affecting the performance of the transistors.

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