Semiconductor device

Abstract

A semiconductor device including: a semiconductor layer including an element formation region including an element; a dielectric layer above the semiconductor; an electrode pad above the dielectric; a passivation layer above the pad and having an opening exposing part of the pad; and a bump in the opening and covering part of the element, the bump including first, second, third and fourth edges, the semiconductor having a forbidden region including: a first distance outward from a first line below the first edge, a second distance inward from the first line, a third distance outward from a second line below the second edge, a fourth distance inward from the second line, a fifth distance outward from a third line below the third edge, a sixth distance inward from the third line, a seventh distance outward from a fourth line below the fourth edge, and an eighth distance inward from the fourth line.

Description

[0001]This application is a divisional of U.S. patent application Ser. No. 11 / 478,485 filed on Jun. 29, 2006. This application claims the benefit of Japanese Patent Application No. 2005-197927, filed on Jul. 6, 2005, and Japanese Patent Application No. 2006-74732, filed on Mar. 17, 2006. The disclosures of the above applications are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]The present invention relates to a semiconductor device.[0003]In related-art technology, when disposing a semiconductor element such as a MOS transistor under a pad, the characteristics of the semiconductor element may be impaired due to stress during bonding. Therefore, the pad formation region and the semiconductor element formation region are separately provided in a semiconductor chip when viewed from the top side. However, since the semiconductor chip has been reduced in size and increased in degree of integration, disposition of the semiconductor element under a pad and a bump has be...

AI Technical Summary

Benefits of technology

"The invention provides a semiconductor device with an element formation region and an isolation region, an electrode pad, an interlayer dielectric, an electrode pad, a passivation layer, and a bump. The bump has a specific shape and position in relation to the element formation region. The technical effect of the invention is to provide a semiconductor device with improved electrical performance and reliability."

Problems solved by technology

In related-art technology, when disposing a semiconductor element such as a MOS transistor under a pad, the characteristics of the semiconductor element may be impaired due to stress during bonding.

However, since the semiconductor chip has been reduced in size and increased in degree of integration, disposition of the semiconductor element under a pad and a bump has been in demand.

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