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[0019]One of the objects, features, and advantages in the present invention is that a volatile memory data cache subsystem is placed between a host and a data storage made of non-volatile memory to reduce data programming to the non-volatile memory, hence prolonging life span of t
Problems solved by technology
However, there are problems associated with using flash memory.
One of the main problems is that the life span of the flash memory is measured by number of times that the flash memory has been written (i.e., programmed) an
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[0043]In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will become obvious to those skilled in the art that the present invention may be practiced without these specific details. The descriptions and representations herein are the common means used by those experienced or skilled in the art to most effectively convey the substance of their work to others skilled in the art. In other instances, well-known methods, procedures, components, and circuitry have not been described in detail to avoid unnecessarily obscuring aspects of the present invention.
[0044]Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily ...
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Abstract
High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation-in-part (CIP) of co-pending U.S. patent application for “High Speed Controller for Phase Change Memory Peripheral Devices”, U.S. application Ser. No. 11 / 770,642, filed on Jun. 28, 2007, which is a CIP of “Local Bank Write Buffers for Acceleration a Phase Change Memory”, U.S. application Ser. No. 11 / 748,595, filed May 15, 2007, which is CIP of “Flash Memory System with a High Speed Flash Controller”, application Ser. No. 10 / 818,653, filed Apr. 5, 2004, now U.S. Pat. No. 7,243,185.[0002]This application is also a CIP of U.S. patent application for “Method and Systems of Managing Memory Addresses in a Large Capacity Multi-Level Cell (MLC) based Memory Devices”, U.S. application Ser. No. 12 / 025,706, filed Feb. 4, 2008.[0003]This application is also a CIP of U.S. patent application for “Hybrid SSD using a combination of SLC and MLC flash memory arrays”, U.S. application Ser. No. 11 / 926,743, filed Oct. 29, 200...
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