Processor and compiler for decoding an instruction and executing the instruction with conditional execution flags

Abstract

The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C6,C1:C4,TAR,Ra”, the processor (i) sets a conditional flag C4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C2 to a conditional flag C1, moves the value of a conditional flag C3 to the conditional flag C2, and moves the value of the conditional flag C4 to the conditional flags C3 and C6, (iii) adds −1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.

Description

[0001]This is a Rule 1.53(b) Divisional of Ser. No. 10 / 805,381, filed Mar. 22, 2004BACKGROUND OF THE INVENTION[0002](1) Field of the Invention[0003]The present invention relates to a processor such as a DSP (Digital Signal Processor) and a CPU (Central Processing Unit), as well as to a compiler that generates instructions executed by such a processor. More particularly, the present invention relates to a processor and a compiler which are suitable for performing signal processing for sounds, images and others.[0004](2) Description of the Related Art[0005]With the development in multimedia technologies, processors are increasingly required to be capable of high-speed media processing represented by sound and image signal processing. As existing processors responding to such requirement, there exist Pentium® / Pentium® III / Pentium 4® MMX / SSE / SSE2 and others produced by the Intel Corporation of the United States supporting SIMD (Single Instruction Multiple Data) instructions. Of these pr...

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Benefits of technology

[0010]The present invention has been conceived in view of the above circumstances, and it is an object of the present invention to provide a processor whose circuitry scale is small and which is capable of performing loop processing at a high speed while consuming a low amount of power.

[0012]As described above, a judgment is made as to whether or not the loop iteration has terminated, based on a conditional execution flag in the epilog phase in the case where such loop is unrolled into conditional execution instructions by means of software pipelining. Accordingly, there is no need to use special hardware resources such as a counter in order to judge whether or not the loop processing has terminated, and it becomes possible to prevent the circuitry scale from becoming large. This contributes to a reduction in the power consumption of the processor.

[0014]As described above, a judgment is made as to whether or not the loop has terminated by use of the value of a conditional execution flag that is specified according to which stage the software pipelining such conditional execution flag is in. Accordingly, there is no need to use special hardware resources such as a counter in order to judge whether or not the loop processing has terminated, and it becomes possible to prevent the circuitry scale from becoming large, regardless of how many stages are contained in software pipelining. This contributes to a reduction in the power consumption of the processor.

[0016]As described above, once a conditional execution instruction stops being executed in the epilog phase, the conditional execution instruction will not be executed in the software pipelining until the loop processing ends. Accordingly, there is no need to read out the conditional execution instruction from the corresponding instruction buffer, which makes it possible for the processor to consume a small amount of power.

[0018]As described above, an instruction to be executed immediately before a loop is placed in the prolog phase in the case where such loop is unrolled by means of software pipelining. Accordingly, it becomes possible to reduce the number of empty stages in the software pipelining, and therefore to execute a program at a high speed. Furthermore, it also becomes possible to reduce the amount of power consumption of a processor that executes a program compiled by this compiler.

[0020]As described above, even when an instruction to be executed when a predetermined condition is met and an instruction to be executed when the condition is not met are different as in the case of an if-else statement in the C language, for example, different flags to be used as predicates shall be associated with the respective instructions. Accordingly, it becomes possible to implement processing which is equivalent to a conditional branch instruction, simply by changing flag values. Since it is possible to realize a conditional branch instruction through such simple processing, it becomes possible to reduce the amount of power consumed by a processor that executes a program compiled by this compiler.

Problems solved by technology

Therefore, such processor is required to be equipped with many resources, which results in large-scale circuits.

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