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Semiconductor device and method of manufacturing semiconductor device

a semiconductor and semiconductor technology, applied in the direction of semiconductor devices, basic electric elements, electrical appliances, etc., can solve the problems of gate electrodes that cannot be easily fully silicided, gate electrodes with a large gate length and a large gate width tend to be silicided, and the thickness reduction of the gate oxide film disadvantageously depletes the gate electrod

Inactive Publication Date: 2008-12-18
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor device and a method of manufacturing the same that solves the problem of uneven gate length or width between different gate electrodes. The semiconductor device includes a semiconductor substrate, a first gate insulation film, a second gate insulation film, a first gate electrode, and a second gate electrode. The second gate electrode has a larger area than the first gate electrode and is fully silicided. The method of manufacturing the semiconductor device includes preparing the semiconductor substrate, depositing a metal film on the substrate, and fully siliciding the first and second gate electrodes. The technical effect of the invention is to provide a semiconductor device with uniform gate length or width between different gate electrodes.

Problems solved by technology

With the micropatterning of devices, gate oxide films are reduced in thickness. when a gate electrode consists of polysilicon, a reduction in thickness of the gate oxide film disadvantageously depletes a gate electrode in switching of a gate electrode.
However, it is known that, when gate electrodes having various gate lengths or gate widths are formed on the same semiconductor substrate, all the gate electrodes cannot be easily fully silicided (see J. Kedzierski et al., IEDM Tech. Dig. (2003)).
However, in contrast to this, a gate electrode having a large gate length and a large gate width tends to be silicided.
When a gate electrode, which is fully silicided, and a gate electrode, which is not fully silicided, are arranged on the same chip, the operation of the semiconductor device disadvantageously fluctuates.
However, such a method makes manufacturing processes cumbersome and elongates a manufacturing period.
As a result, the cost of the semiconductor increases.

Method used

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  • Semiconductor device and method of manufacturing semiconductor device
  • Semiconductor device and method of manufacturing semiconductor device
  • Semiconductor device and method of manufacturing semiconductor device

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Experimental program
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Effect test

first embodiment

[0056]FIG. 1 is a sectional diagram of a semiconductor device 100 according to the first embodiment of the present invention. FIG. 1 shows two MIS transistors 101 and 102 having lengths different from each other. It is assumed that the gate widths of the MIS transistor 101 and the MIS transistor 102 are equal to each other. The MIS transistors 101 and 102 may be p-type transistors or n-type transistors. In the first embodiment, gate electrodes are controlled in thickness to fully silicide a plurality of gate electrodes having different gate lengths.

[0057]The semiconductor device 100 includes a semiconductor substrate 5, a source-drain silicide layer 10, an STI (Shallow Trench Isolation) 20, a side wall 30, a source-drain diffusion layer 40, a first gate insulation film 51, a second gate insulation film 52, a first gate electrode 11, and a second gate electrode 12.

[0058]The STI 20 performs device isolation between the MIS transistors 101 and 102. The first gate insulation film 51 and...

second embodiment

[0074]FIG. 6 is a sectional diagram of a semiconductor device 200 according to the second embodiment of the present invention. In the second embodiment, an MIS transistor 102 is formed on a semiconductor region 90 formed on a semiconductor substrate 5. Therefore, the bottom surface of the second gate electrode 12 is set at a higher level from the surface 7 of the semiconductor substrate 5 than the bottom surface of the first gate electrode 11. As a result, the upper surface of the second gate electrode 12 can be set at a level equal to the upper surface of the first gate electrode 11, and the thickness of the second gate electrode 12 is smaller than the thickness of the first gate electrode 11. The other constitution in the second embodiment may be the same as that in the first embodiment.

[0075]The semiconductor region 90 consists of, e.g., silicon single crystal. The thickness of the semiconductor region 90 may be equal to a difference between the thickness of the first gate electr...

third embodiment

[0089]FIG. 11 is a sectional diagram of a semiconductor device 300 according to the third embodiment of the present invention. In the third embodiment, a second gate electrode 12 includes a plurality of sub-gate electrodes 301 and a plurality of inter-electrode insulation films 302. The plurality of sub-gate electrodes 301 are parallel formed on a second gate insulation film. The inter-electrode insulation film 302 is formed between the adjacent sub-gate electrodes 301. Therefore, the sub-gate electrodes 301 and the inter-electrode insulation films 302 are alternately formed to give the appearance that the sub-gate electrodes 301 and the inter-electrode insulation films 302 have a striped shape on the section or the upper surface.

[0090]The gate length of the first gate electrode 11 is 20 nm, for example. The gate length of the second gate electrode 12 is 120 nm, for example. The width of the sub-gate electrode 301 is 20 nm, for example. The width of the inter-electrode insulation fi...

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Abstract

A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate; a first gate electrode formed on the first gate insulation film and fully silicided; and a second gate electrode formed on the second gate insulation film and fully silicided, a gate length or a gate width of the second gate electrode being larger than that of the first gate electrode, and a thickness of the second gate electrode being smaller than that of the first gate electrode.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2005-19293, filed on Jan. 27, 2005, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.[0004]2. Background Art[0005]In order to obtain a high-performance CMIS device, micropatterning of devices advances. With the micropatterning of devices, gate oxide films are reduced in thickness. when a gate electrode consists of polysilicon, a reduction in thickness of the gate oxide film disadvantageously depletes a gate electrode in switching of a gate electrode. When the thickness of the gate oxide film is lower than 1 nm, a percentage of a depletion capacity of the gate electrode to the capacity of the gate oxide film reaches 30%.[0006]In order to co...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/08
CPCH01L21/28097H01L21/28105H01L21/32155H01L21/82385H01L29/66651H01L29/785
Inventor KINOSHITA, ATSUHIROTSUCHIYA, YOSHINORIKOGA, JUNJI
Owner KK TOSHIBA