Delay calculation method capable of calculating delay time with small margin of error

Abstract

A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t0, increases to V1 during Δt1; and the one indicating that the voltage increases from V1 to E during Δt2 and thereafter remains at the fixed value of E. A difference in the shapes of input waveforms is adopted as a correction parameter to determine the values of Δt1, V1, and Δt2.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a delay calculation method for calculating delay time of, for example, each macrocell with transistors.[0003]2. Description of the Background Art[0004]For timing verification of semiconductor integrated circuits (SOC: System on Chip) equipped with large-scale systems, delay time in each instance must be calculated with accuracy. One of well-known high-precision delay calculation methods is that using circuit simulations such as SPICE. In circuit simulations, the analysis of operating points of each device is made on matrix calculation. This calculation is conducted at each lapse of a very short time to obtain a voltage value at every node. In this technique, a huge matrix must be analyzed for the analysis of operation at a certain time, so an increase in the number of devices will markedly increase the amount of calculation. Further, the necessity of conducting matrix calculation at each...

AI Technical Summary

Benefits of technology

This method allows for precise delay time calculations with a small margin of error, improving the accuracy of circuit design by considering the shape of input waveforms and output load capacitance, thus enhancing the reliability of semiconductor integrated circuits.

Problems solved by technology

Further, the necessity of conducting matrix calculation at each lapse of a very short time makes impossible to conduct an analysis within a realistic time, for semiconductor integrated circuits which include an extremely large number of devices such as large-scale SOCs.

Consequently, the results of delay calculations in conventional delay calculation methods have a margin of error of around 8 percent even if parameters are optimized somehow.

From this, the 8-percent inherent margin of error has made circuit design difficult.

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