Ring oscillator and multi-phase clock correction circuit using the same

Abstract

A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]The present invention claims priority from Korean patent application number 10-2008-0063134, filed on Jun. 30, 2008, which is incorporated by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates to a semiconductor design technology, and more particularly, to a ring oscillator for generating an oscillating clock signal and a multi-phase clock correction circuit for correcting the phase of a multi-phase clock signal using the same. In general, a semiconductor device, such as Double Data Rate Synchronous DRAM (DDR SDRAM), includes diverse circuits for performing a variety of circuit operations. As one of these diverse circuits, there is a ring oscillator. Typically, the ring oscillator is provided with an odd number of inverters to generate an oscillating clock signal. Recently, however, a ring oscillator with an even number of inverters as shown in FIG. 1 has been mainly employed.[0003]Referring to the cir...

AI Technical Summary

Benefits of technology

[0012]The ring oscillator in accordance with the invention employs a plurality of buffers having a cross-coupled structure, which is capable of generating clock signals of a CML level, thereby generating clock signals that consume less power in a high speed operation and have low jitter characteristics. In addition, the ring oscillator in accordanc...

Problems solved by technology

However, the existing ring oscillator by its configuration has to generate a CMOS level clock signal rather than a CML level clock signal, and thus, it is not suitable for semiconductor devices of current design.

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