Self-testing and -repairing fault-tolerance infrastructure for computer systems

a fault-tolerance infrastructure and computer system technology, applied in error detection/correction, redundancy hardware error correction, instruments, etc., can solve problems such as no absolute prevention or guarantee, and achieve the effect of enhancing reliability

Inactive Publication Date: 2010-08-26
AVIZIENIS ALGIRDAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0079]In particular, whereas the earlier-discussed fifth aspect of the invention enhances reliability through comparison of processing results among subsystems within the protected computing system, this seventh facet of the invention looks to comparison of modules in the protective apparatus itself—to attain an analogous upward step in reliability of the hybrid overall system.

Problems solved by technology

(The term “deterring” implies that the computing system is rendered less probable to fail, but there is no absolute prevention or guarantee.)

Method used

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  • Self-testing and -repairing fault-tolerance infrastructure for computer systems
  • Self-testing and -repairing fault-tolerance infrastructure for computer systems
  • Self-testing and -repairing fault-tolerance infrastructure for computer systems

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Embodiment Construction

1. System Elements

[0098]Preferred embodiments of the present invention provide a so-called “fault-tolerance infrastructure” (FTI) that is a system composed of four types of special-purpose controllers which will be called “nodes”. The nodes are ASICs (application-specific integrated circuits) that are controlled by hardwired sequencers or by microcode.

[0099]The preferred embodiments employ no software. The four kinds of nodes will be called:

[0100](1) A-nodes (adapter nodes);

[0101](2) M-nodes (monitor nodes);

[0102](3) D-nodes (decision nodes); and

[0103](4) S3-nodes (startup, shutdown, and survival nodes).

[0104]The purpose of the FTI is to provide protection against all five causes of system failure for a computing system that can be substantially conventional and composed of COTS components, called C-nodes (computing nodes). Merely for the sake of simplicity—and tutorial clarity in emphasizing the capabilities of the invention this document generally refers to the C-nodes as made up ...

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Abstract

ASICs or like fabrication-preprogrammed hardware provide controlled power and recovery signals to a computing system that is made up of commercial, off-the-shelf components—and that has its own conventional hardware and software fault-protection systems, but these are vulnerable to failure due to external and internal events, bugs, human malice and operator error. The computing system preferably includes processors and programming that are diverse in design and source. The hardware infrastructure uses triple modular redundancy to test itself as well as the computing system, and to remove failed elements—powering up and loading data into spares. The hardware is very simplified in design and programs, so that bugs can be thoroughly rooted out. Communications between the protected system and the hardware are protected by very simple circuits with duplex redundancy.

Description

BACKGROUND[0001]1. Field of the Invention[0002]This invention relates generally to robustness (resistance to failure) in computer systems; and more particularly to novel apparatus and methods for shielding and preserving computer systems—which can be substantially conventional systems—from failure.[0003]2. Related Art[0004](a) Earlier publications—Listed below, and wholly incorporated by reference into the present document, are earher materials in this field that will be helpful in orienting the reader. Cross-references to these publications, by number in the following list, appear enclosed in square brackets in the present document:[0005][1] Intel Corp., Intel's Quality System Databook (January 1998), Order No. 210997-007.[0006][2] A. Avi{hacek over (z)}ienis and Y. He, “Microprocessor entomology: A taxonomy of design faults in COTS microprocessors”, in J. Rushby and C. B. Weinstock, editors, Dependable Computing for Critical Applications 7, IEEE Computer Society Press (1999).[0007...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F11/20G06F11/07G06F11/30
CPCG06F11/2028G06F11/183
Inventor AVIZIENIS, ALGIRDAS
Owner AVIZIENIS ALGIRDAS
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