This invention discloses a hardware fault control method and
system based on a
motor controller. The method includes configuring a hardware fault
signal as an interrupt trigger input for the
microcontroller; after
system power-on initialization, resetting the driver
chip and then enabling the hardware latch circuit, which latches the hardware fault
signal and outputs a total hardware fault
signal; monitoring the hardware fault signal, and when the trigger edge of the hardware fault pin is interrupted, determining whether the current motor state meets preset conditions; if the conditions are met, setting the corresponding
software fault flag; acquiring the
software fault flag and the total hardware fault signal output by the hardware latch circuit, and combining this with whether the motor is currently under high-
voltage power-on, performing fault diagnosis and corresponding protection and
recovery operations. This invention solves the technical problems of slow hardware fault diagnosis response speed, easy false alarms during power-on, and limited fault
recovery strategies in existing technologies.